XRT74L73 Datasheet, PDF (131/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
To determine the framing state that the Receive
PLCP Processor is operating in, read bits 1 and 2 of
the Receive PLCP Configuration Status Register. The
bit-format of this register is presented below.
RxPLCP Configuration/Status Register (Address = 44h)
BIT 7
RO
BIT 6
BIT 5
Unused
RO
RO
BIT 4
RO
BIT 3
Reframe
R/W
BIT 2
POOF Status
RO
BIT 1
PLOF Status
RO
BIT 0
Yellow Status
RO
Bit 1—PLOF Status
A “1” in this bit-field indicates a “Loss of Frame” status.
Consequently, the Receive PLCP Processor will be
operating in the “Un-framed” state. Conversely, a “0”
in this bit-field indicates that the Receive PLCP
Processor is either in the “In-Frame” or “Out-of-
Frame” state.
Note: the state of this bit-field (and the RxLOF output pin)
is controlled by the contents of an Up/Down Counter. This
counter is incremented whenever the “POOF Status” bit is
“1” and is decremented when the “POOF Status bit is ‘0’.
However, the counter is decremented at 1/12th of the rate
that it is incremented. Therefore, when the Receive PLCP
Processor goes into the “OOF” condition, this Up/Down
Counter will increment. If the Receive PLCP Processor
requires 1ms to regain Frame-Synchronization, the PLOF
bit-field might very well be asserted, denoting an “LOF con-
dition”. However, even after the Receive PLCP Processor
has declared itself “In-Frame”, the PLOF bit-field will not be
negated until the POOF bit-field has been negated for 12 ms.
Bit 2—POOF Status
A “1” in this bit-field indicates an “Out-of-Frame”
condition. This condition necessarily indicates that
the Receive PLCP Processor is not in the “In-frame”
condition. Therefore, the user will have to read-in the
value of bit 1 in order to determine if the Receive
PLCP Processor is operating in the “Out-of-Frame” or
“Un-Framed” state.
The following table relates the “read-in” values for bits
1 and 2 to the framing state of the Receive PLCP
Processor.
TABLE 20: THE RELATIONSHIP BETWEEN THE LOGIC STATES OF THE POOF AND PLOF BIT-FIELDS, AND THE
CORRESPONDING RECEIVE PLCP FRAMING STATE
POOF BIT 2
0
0
1
1
PLOF BIT 1
0
1
0
1
RECEIVE PLCP FRAMING STATE
In-Frame
In-Frame—PLOF is still “1” during the “12 ms period” that POOF is “0”
Out of Frame
Un-frame
3.2.2.1.4Reframe via Software Command
The Receive PLCP Processor can be forced into the
“OOF” mode, via software command. This is accom-
plished by writing a “1” to Bit 3 in the RxPLCP Config-
uration/Status Register, as depicted below.
RxPLCP Configuration/Status Register (Address = 44h)
BIT 7
x
BIT 6
BIT 5
Unused
x
x
BIT 4
x
BIT 3
Reframe
1
BIT 2
POOF Status
x
BIT 1
PLOF Status
x
BIT 0
Yellow Status
x
3.2.2.2Overhead Byte Processing
Once the Receive PLCP Processor enters into the “In-
frame” mode, the 12 POH bytes are then extracted
and output via a serial output port. Presently, the Re-
ceive PLCP Processor is only concerned with three
(3) of these POH bytes: B1, G1, and C1. The manner
in which the Receive PLCP Processor handles these
POH bytes follows.
3.2.2.2.1B1 (BIP-8) Byte
The Receive PLCP Processor will perform a BIP-8
calculation over an entire PLCP frame (excluding the
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