XRT74L73 Datasheet, PDF (24/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
K3
K2
K1
NAME
TxNib_2_0/
TxStuffCtl_0/
TxHDLCDat_2_0
TxNib_2_1/
TxStuffCtl_1/
TxHDLCDat_2_1
TxNib_2_2/
TxStuffCtl_2/
TxHDLCDat_2_2
TYPE
I
DESCRIPTION
Transmit Nibble Input Interface - Bit 2/Transmit PLCP Stuff Control Input/
Transmit HDLC Controller Data Bus - Bit 2 Input:
The exact function of this input pin depends upon whether the XRT74L73 device
is configured to operate in the Clear-Channel Framer Mode, the High-Speed
HDLC Controller Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_2_n:
If the user opts to operate the XRT74L73 device in the Nibble-Parallel Mode,
then this input pin will function as the bit 1 input to the "Transmit Nibble-Parallel"
input interface. The Transmit Payload Data Input Interface block will sample this
signal (along with TxNib_0_n, TxNib_2_n and TxNib_3_n) upon the falling edge
of TxNibClk_n
NOTE: This input pin is inactive if the Channel is configured to operate in the
"Serial" Mode.
ATM/PLCP Mode - TxStuffCtl_n:
This input pin permits the user to externally exercise or forego trailer nibble stuff-
ing opportunities by the Transmit PLCP Processor. PLCP trailer nibble stuff
opportunities occur in periods of three PLCP frames (375 us). The first PLCP
frame (first, within a "stuff opportunity period) will have 13 trailer nibbles
appended to it. The second PLCP frame (second within a "stuff opportunity"
period) will have 14 trailer nibbles appended to it. The third PLCP frame (the
location of the stuff opportunity) will contain 13 trailer nibbles if this input pin is
pulled "low", and 14 trailer nibbles if this input pin is pulled "high".
NOTE: This input pin is inactive if the XRT74L73 device is configured to operate
in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_2_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 1"
within this byte wide interface. Data residing on the "Transmit HDLC Controller"
byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
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