XRT74L73 Datasheet, PDF (242/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
• The Receive DS3 Framer will assert the RxOOF
output pin (e.g., toggles it "High").
Rx DS3 Configuration and Status Register, (Address
= 0x10)
• Bit 4 (RxOOF) within the Rx DS3 Configuration and
Status Register will be set to "1" as depicted below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
RxAIS
RxLOS
RxIdle
RxOOF
Int LOS
Disable
Framing on F-Sync Algo M-Sync Algo
Parity
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
• The Receive DS3 Framer block will also issue a
Change in OOF Status interrupt request, anytime
there is a change in the OOF status.
4.3.2.3 Forcing a Reframe via Software Com-
mand
The Framer IC permits the user to force a reframe
procedure of the Receive DS3 Framer block via soft-
ware command. If a "1" is written into Bit 0 of the I/O
I/O CONTROL REGISTER (ADDRESS = 0X01)
Control Register, as depicted below, then the Receive
DS3 Framer will be forced into the Frame Acquisition
Mode, (or more specifically, in the F-Bit Search State
per Figure 88 ). Afterwards, the Receive DS3 Framer
block will begin its search for valid F-Bits. The Fram-
er IC will also respond to this command by asserting
the RxOOF output pin, and generating a Change in
OOF Status interrupt.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
LOC
Disable
RxLOC
AMI/ZeroSup* Unipolar/
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
1
4.3.2.4 Performance Monitoring of the Receive
DS3 Framer block
The user can monitor the number of framing bit errors
(M and F bits) that have been detected by the Re-
ceive DS3 Framer block. This is accomplished by pe-
riodically reading the PMON Framing Bit Error Count
Registers (Address = 0x52 and 0x53), as depicted
below.
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
RUR
1
BIT 6
RUR
0
BIT 5
RUR
1
BIT 4
BIT 3
F-Bit Error Count - High Byte
RUR
RUR
0
0
BIT2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
F-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
BIT 0
RUR
0
243