XRT74L73 Datasheet, PDF (22/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
M24
M25
M26
NAME
RxPOHClk_0/
RxClk_0/
RxNibClk_0
RxPOHClk_1/
RxClk_1/
RxNibClk_1
RxPOHClk_2/
RxClk_2/
RxNibClk_2
B3
RxPOS_0
C10
RxPOS_1
C19
RxPOS_2
TYPE
O
I
DESCRIPTION
Receive PLCP Path Overhead Serial and Nibble-Parallel Output port clock/
Receive Serial Clock output:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the ATM/PLCP Mode, the Clear-Channel Framer
Mode, or not.
ATM/PLCP Mode - RxPOH_Clk_n:
This output clock pin, along with "RxPOH_n", "RxPOHFrame_n" and
"RxPOHIns_n" pins comprise the "Receive PLCP Frame POH Byte" serial output
port. All POH (Path Overhead) data that is output via the "RxPOH_n" output pin
is updated on the rising edge of this clock signal.
NOTE: This output signal is inactive if the XRT74L73 device has been configured
to operate in the Direct-Mapped ATM Mode.
Clear-Channel Framer Mode - RxClk_n:
This output pin is active whenever the channel has been configured to operate in
either the Serial or Nibble Parallel Mode.
Clear-Channel Framer/Serial Mode - RxClk_n:
In this "serial" mode, this output is a 44.736MHz clock output signal (for DS3
applications) or 34.368MHz clock output signal (for E3 applications). The
Receive Payload Data Output Interface will update the data via the RxSer_n out-
put pin, upon the rising edge of this clock signal.The user is advised to design (or
configure) the local terminal equipment to sample the "RxSer_n" data, upon the
falling edge of this clock signal.
Clear-Channel Framer/Nibble-Parallel Mode - RxSer_n:
In the Nibble-Parallel Mode, the XRT74L73 device will derive this clock signal
from the "RxLineClk_n" signal. The XRT74L73 device will pulse this clock signal
1176 times for each "inbound" DS3 frame (or 1074 times for each inbound E3/
ITU-T G.832 frame or 384 times for each inbound E3/ITU-T G.751 frame). The
Receive Payload Data Output Interface block will update the data (on the
RxNib_n[2:0] output) upon the falling edge of this clock signal.The user is
advised to design (or configure) the local terminal equipment to sample the data
on the "RxNib[2:0]" output pins, upon the rising edge of this clock signal.
Receive Positive Polarity Data Input:
The exact function of these input pins depend upon whether the XRT74L73
device is operating in the Single-Rail or Dual-Rail Mode.
Single-Rail Mode:
This input pin functions as the "Single-Rail" (e.g., binary data stream) input for
the incoming DS3 or E3 data stream. This signal at this input pin will be sampled
and latched upon the "user-selected" edge of the RxLineClk_n signal.
Dual-Rail Mode:
This input pin functions as one of the dual-rail inputs for the incoming B3ZS/
HDB3 encoded DS3 or E3 data, which as been received the external LIU IC.
RxNEG_n functions as the other dual-rail input for the Framer/UNI IC. When this
input pin is pulse "high", it means that the LIU IC has received a positive polarity
pulse from the line.
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