XRT74L73 Datasheet, PDF (132/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
A1, A2 and POI bytes) that it receives from the
Receive DS3 Framer. Afterwards, the Receive PLCP
Processor will read in the B1 byte, of the very next
incoming PLCP frame, and perform a bit-by-bit
comparison between this B1 byte and this locally-
computed BIP-8 value. By the nature of the BIP-8 val-
ues, it is possible to have as many as 8 bit errors in
this comparison. If the Receive PLCP Processor de-
tects any BIP-8 errors, then it will do two things:
• increment the PMON BIP-8 Error Count Registers
(Address = 28h and 29h) by the number of detected
bit-errors, and,
• Inform the “Far-End” Terminal (e.g., the source of the
errored data) of this occurrence by routing the number of
bit-errors that were detected in this frame to the “Near-
End” Transmit PLCP Processor. The Transmit PLCP
Processor will then insert this number into the FEBE-
nibble within the G1 byte of an outbound PLCP frame.
Then the outbound PLCP frame (containing the informa-
tion on the B1 byte error) will be transmitted to the “Far-
End” terminal where it will be processed appropriately.
Table 21 presents the bit format of the G1 byte. The
Receive PLCP processor performs this function in
order to inform the “Far-End Terminal that bit errors
have been detected in its transmission.
TABLE 21: BIT FORMAT OF THE G1 BYTE
BIT 7
BIT 6
BIT 5
Far End Block Error (FEBE)
4 Bits
BIT 4
BIT 3
RAI (Yellow)
1 Bit
BIT 2
BIT 1
BIT 0
X bits (Ignored by the Receiver)
3 Bits
The bit-format of the PMON BIP-8 Error Count Regis-
ter (Address = 28h and 29h) are presented below.
Address = 28h, PMON BIP-8 Error Count Register—MSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
BIP-8 Error Count—High Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
Address = 29h, PMON BIP-8 Error Count Register—LSB
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
BIP-8 Error Count—Low Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
The contents of these registers reflect the total num-
ber of BIP-8 Errors that have been detected since the
last read of these registers. These registers are reset
upon read.
3.2.2.2.2G1 Byte
The incoming G1 Byte serves to provide the “Near-End”
Terminal with diagnostic information on the quality of
the transmission link between the “Near-End” Transmit
PLCP Processor and the “Far-End” Receive PLCP
Processor. The bit-format of the G1 byte, presented
in Table 21 , indicates that 5 of the 8 bits in this byte
are relevant to transmission diagnosis.
Bit 3—RAI—Yellow Alarm Indicator
This bit-field serves as a “Yellow Alarm” indicator. The
“Far-End” Transmit PLCP Processor will assert this
bit-field if the “Far End” Receive PLCP Processor has
had sufficient trouble receiving valid data from the
“Near-End” Transmit PLCP Processor; and that this
condition has persisted for 2 to 10 seconds. If this bit-
field is asserted for 10 consecutive incoming PLCP
frames then the Receive PLCP Processor will assert
the “Yellow Alarm” status bit (Bit 0) within the Receive
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