XRT74L73 Datasheet, PDF (15/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
E4
TxInClk_0
G4
TxInClk_1
F2
TxInClk_2
F3
TxOH_0/
TxHDLCDat_5_0
F1
TxOH_1/
TxHDLCDat_5_1
G3
TxOH_2/
TxHDLCDat_5_2
B6
TxOHClk_0
A6
TxOHClk_1
C5
TxOHClk_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
I
I
O
DESCRIPTION
Transmit DS3 Framer Block—Clock Signal:
If the Transmit Section of a given channel (within the XRT74L73 device) is con-
figured to operate in the Local-Timing Mode, then it will use this signal as the
Timing Reference. If the user is operating a channel in the DS3 Mode, then user
is expected to apply a high-quality 44.736MHz clock signal to this input pin.
Likewise, if the user is operating a channel in the E3 Mode, then the user is
expected to apply a high-quality 34.368MHz clock signal to this input pin.A
Note for Clear-Channel Framer Operation:
If the user is operating the XRT74L73 device in the Clear-Channel Framer
mode, then the user should design the local terminal equipment circuitry, such
that "outbound" DS3 or E3 data will be output, upon the falling edge of TxInClk.
The Transmit Payload Data Input Interface (within the Transmit Section of the
XRT74L73 device) will sample the data, applied to the "TxSer" input pin, upon
the rising edge of TxInClk.
NOTE: This input pin should be tied to GND if the XRT74L73 device is config-
ured to operate in the "Loop-Timing" Mode.
Transmit Overhead Input Pin/Transmit HDLC Controller Data Bit 5:
The function of these input pins depends upon whether the channel has been
configured to operate in the High Speed HDLC Controller Mode or not.
Non-High Speed HDLC Controller Mode - TxOH_n:
The Transmit Overhead Data Input Interface accepts overhead via these input
pins, and insert this data into the "overhead" bit positions within the outbound
DS3 or E3 frames. If the "TxOHIns_n" input pin is pulled "high", then the Trans-
mit Overhead Data Input Interface will sample the overhead data, via this input
pin, upon the falling edge of the TxOHClk_n output signal. Conversely, if the
TxOHIns_n input pin is NOT pulled "high", then the Transmit Overhead Data
Input Interface block will be inactive and will not accept any overhead data via
the TxOH_n input pin.
High Speed HDLC Controller Mode - TxHDLCDat_5_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 5"
within this byte wide interface. Data, residing on the "Transmit HDLC Controller"
byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
Transmit Overhead Clock:
This output pin functions as the "Transmit Overhead Data Input Interface clock
signal. If the user enables the "Transmit Overhead Data Input Interface" block by
asserting the "TxOHIns" input pin, then the Transmit Overhead Data Input Inter-
face block will sample and latch the data (residing on the "TxOH_n" input pin)
upon the falling edge of this signal.
NOTE: The Transmit Overhead Data Input Interface block is disabled if the user
has configured the channel to operate in the "High-Speed HDLC Controller"
Mode.
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