XRT74L73 Datasheet, PDF (189/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
3. Interface the XRT74L73, to the Terminal Equip-
ment, as illustrated in Figure 53 .
4.2.1.3 Mode 3 - The Serial/Local-Timed/
Frame-Master Mode Behavior of the XRT74L73
If the XRT74L73 has been configured to operate in
this mode, then the XRT74L73 will function as fol-
lows.
A. Local Timing - (Uses the TxInClk signal as the
Timing Reference)
In this mode, the Transmit Section of the XRT74L73
will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT74L73 will receive the DS3 payload data, in
a serial manner, via the TxSer input pin. The Trans-
mit Payload Data Input Interface (within the
XRT74L73) will latch this data into its circuitry, on the
rising edge of the TxInClk input clock signal.
C. Delineation of outbound DS3 frames (Frame
Master Mode)
The Transmit Section of the XRT74L73 will use the
TxInClk signal as its timing reference, and will initiate
DS3 frame generation, asynchronously with respect
to any externally applied signal. The XRT74L73 will
pulse its TxFrame output pin "High" whenever it is
processing the very last bit-field within a given DS3
frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 3, the XRT74L73 will sample the data, at the
TxSer input pin, on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT74L73 to the Terminal Equip-
ment for Mode 3 Operation
Figure 55 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT74L73) being interfaced to the Terminal Equip-
ment, for Mode 3 operation.
FIGURE 55. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT74L73 FOR MODE 3 (SERIAL/LOCAL-TIMED/FRAME-MASTER) OPERATION
44.736 MHz Clock
Source
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
Terminal Equipment
TxInClk
TxSer
TxFrame
TxOH_Ind
NibIntf
XRT72L5x DS3 Framer
Mode 3 Operation of the Terminal Equipment
In Figure 55 , both the Terminal Equipment and the
XRT74L73 are driven by an external 44.736MHz
clock signal. This clock signal is connected to the
DS3_Clock_In input of the Terminal Equipment and
the TxInClk input pin of the XRT74L73.
The Terminal Equipment will serially output the pay-
load data on its DS3_Data_Out output pin, upon the
rising edge of the signal at the DS3_Clock_In input
pin. Similarly, the XRT74L73 will latch the data, re-
siding on the TxSer input pin, on the rising edge of
TxInClk.
The XRT74L73 will pulse the TxFrame output pin
"High" for one bit-period, coincident while it is pro-
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