XRT74L73 Datasheet, PDF (124/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
3.0THE RECEIVE SECTION
The purpose of the Receiver Section of the
XRT74L73 DS3/E3 ATM UNI is to allow a local ATM
Layer (or ATM Adaptation Layer) processor to receive
ATM cell data from a remote piece of equipment via a
public or leased DS3 transport medium.
The Receive Section of the DS3 UNI chip consists of
the following functional blocks:
• Receive DS3 Framer
• Receive PLCP Processor
• Receive Cell Processor
• Receive UTOPIA Interface
The Receive DS3 Framer will synchronize itself to
this incoming DS3 Data Stream (containing ATM
cells) via the RxPOS, RxNEG, and RxLineClk input
pins, and proceed to “strip off” and process the OH
bits of the DS3 frame. Once all of the OH bits have
been removed, the payload portion of the received
DS3 Frame should consist of either PLCP frames or
ATM cells (if the Direct-Mapped ATM option was se-
lected). The PLCP frames are routed to the Receive
PLCP Processor and the “Direct-Mapped” ATM Cells
are sent onto the Receive Cell Processor.
The Receive PLCP Processor will take the PLCP
frame data and search for the A1/A2 Frame Align-
ment pattern bytes, in order to determine the PLCP
frame boundaries. Once PLCP framing is estab-
lished, the Receive PLCP Processor will proceed to
check and process the OH bytes, within the PLCP
frame. The PLCP Frames, along with framing infor-
mation are sent on to the Receive Cell Processor.
The Receive Cell Processor takes delineated PLCP
frames from the Receive PLCP Processor, and per-
forms the following operations:
• Performs Cell Delineation.
• HEC Byte Verification
It takes the first four octets of the cell (the header)
and computes a HEC byte. The Receive Cell Proces-
sor will then compare this computed HEC value with
that of the fifth octet, within the cell. If the two HEC
values are equal, the cell is then retained for further
processing. If the two HEC values are not equal, then
the cells with single-bit errors are corrected. However,
the cell is optionally discarded if multile-bit errors are
detected.
• Idle Cell Filtering
The Receive Cell Processor will detect and remove
Idle Cells and can be configured to filter User and
OAM cells.
• The Receive Cell Processor will de-scramble the pay-
load portion of the cell (the 6th through the 53rd octet),
and pack these octets in with the cell header bytes, and
the HEC byte for transmission to the Receive UTOPIA
block.
The following sections discuss the blocks comprising
the Receiver portion of the DS3 UNI in detail.
3.1Receive DS3 Framer
3.1.1Brief Description of the Receive DS3 Framer
The Receive DS3 Framer synchronizes itself to the
incoming DS3 data-stream. It decodes and frames
the incoming data into DS3 frames. It supports both
the M13 and C-bit Parity framing formats. It detects
Line Code Violations (LCV), the Loss of Signal (LOS)
condition, the Alarm Indication Signal (AIS) and Idle
patterns, Out of Frame (OOF) and Loss of Frame
(LOF) conditions. The Receive DS3 Framer computes
parity over a given DS3 M-frame and compares it with
the P-bits that it receives in the very next DS3 M‘-
hframe. It extracts and processes the DS3 frame
overhead bits and provides them to a serial output
port. It “validates” FEAC messages received from the
“Far-End” Transmit DS3 Framer. Additionally, the
Receive DS3 Framer will receive “LAPD Messages”
from the “Far End” Transmit DS3 Framer; and will
write this message into the “Receive LAPD Message”
buffer.
The Receive DS3 Framer will detect and generate
interrupts upon error conditions. The status of the Re-
ceive DS3 Framer can be read by registers through
the UNI-Microprocessor interface. If the UNI is oper-
ating in the “Direct-Mapped” ATM Mode, then the Re-
ceive DS3 Framer will route the contents of the DS3
payload to the Receive Cell Processor. Otherwise, if
the UNI is operating in the PLCP mode, then the Re-
ceive DS3 framer will route the payload to the Re-
ceive PLCP Processor.
Figure 21 presents a simple block diagram of the
Receiver DS3 Framer along with the associated pins.
Additionally, Figure 22 presents a more in-depth
functional block diagram of the Receive DS3 Framer.
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