XRT74L73 Datasheet, PDF (171/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TABLE 31: UTOPIA ADDRESS VALUES OF THE UTOPIA INTERFACE BLOCKS ILLUSTRATED IN FIGURE 43
BLOCK
Transmit UTOPIA Interface block—UNI #2
Receive UTOPIA Interface block—UNI #2
UTOPIA ADDRESS VALUE
02h
03h
Recall, that the Receive UTOPIA Interface blocks were
assigned these addresses by writing these values into
the “RxUTOPIA Address Register” (Address = 6Ch)
within their “host” UNI device. The discussion of the
Transmit UTOPIA Interface blocks, within UNIs #1
and #2 is presented in Section 6.1.2.3.2.1.
Polling Operation
Consider that the ATM Layer processor is currently
reading a continuous stream of cells from UNI #1.
While reading this cell data from UNI #1, the ATM
Layer processor can also “poll” UNI #2 for “availability”
(e.g., tries to determine if the RxFIFO within UNI #2,
contains some ATM cell data that needs to be read).
The ATM Layer Processor’s Role in the “Polling” Opera-
tion
The ATM Layer processor accomplishes this “polling”
operation by executing the following steps.
1. Assert the RxUEn input pin (if it not asserted already).
The UNI device (being “polled”) will know that this is
only a “polling” operation, if the RxUEn input pin is as-
serted, prior to detecting its UTOPIA Address on the
“UTOPIA Address” bus.
2. The ATM Layer processor places the address of the
Receive UTOPIA Interface Block of UNI #2 onto the
UTOPIA Address Bus, Ut_Addr[4:0],
3. The ATM Layer processor will then check the value of
its “RxUClav_in” input pin (see Figure 42 ).
The UNI Device’s Role in the “Polling” Operation
UNI #2 will sample the signal levels placed on its
Rx UTOPIA Address input pins (RxUAddr[4:0]) on the
rising edge of its “Receive UTOPIA Interface block”
clock input signal, RxUClk. Afterwards, UNI #2 will
compare the value of these “Receive UTOPIA Address
Bus input pin” signals with that of the contents of its
“RxUTOPIA Address Register” (Address = 6Ch).
If these values do not match (e.g., RxUAddr[4:0] µ
03h) then UNI #2 will keep its “RxUClav” output signal
“tri-stated”; and will continue to sample its “Receive
UTOPIA Address bus input” pins, with each rising
edge of RxUClk.
If these two values do match (e.g., RxUAddr[4:0] =
03h) then UNI #2 will drive its “RxUClav” output pin to
the appropriate level, reflecting its RxFIFO “fill sta-
tus”. Since the UNI is automatically operating in the
“Cell Level Handshaking” mode, while it is operating
in the “Multi-PHY” mode, the UNI will drive the RxU-
Clav output signal “high” if it contains at least one
complete cell of data that needs to be read by the
ATM Layer processor. Conversely, the UNI will drive
the “RxUClav” output signal “low” if its RxFIFO is de-
pleted, or does not contain at least one full cell of da-
ta.
When UNI #2 has been selected for “polling”, UNI #1
will continue to keeps its “RxUClav” output signal “tri-
stated”. Therefore, when UNI #2 is driving its “RxU-
Clav” output pin to the appropriate level; it will be driv-
ing the entire “RxUClav” line, within the “Multi-PHY”
system. Consequently, UNI#1 will also be driving the
“RxUClav_in” input pin of the ATM Layer processor
(see Figure 43 ).
If UNI #2 drives the “RxUClav” line “low”, upon the
application of its address on the UTOPIA Address
bus, then the ATM Layer processor will “learn” that
UNI #2 does not contain any ATM cell data that is
ready to be read. However, if UNI #2 drives the RxU-
Clav line “high” (during “polling”), then the ATM Layer
processor will know that UNI#2 contains at least one
cell of data that needs to be read.
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