XRT74L73 Datasheet, PDF (391/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
The behavior of the signals between the XRT74L73
and the Terminal Equipment for E3 Mode 2 Operation
is illustrated in Figure 167 .
FIGURE 167. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L73 AND THE TERMINAL
EQUIPMENT (MODE 2 OPERATION)
Terminal Equipment Signals
E3_Clock_In
E3_Data_Out
Tx _Start_of_Frame
E3_Overhead_Ind
Payload[4238] Payload[4239]
FA1, Bit 7
FA1, Bit 6
XRT74L73 Transmit Payload Data I/F Signals
TxInClk
TxSer
Payload[4238] Payload[4239]
TxFrameRef
TxOH_Ind
FA1, Bit 7
FA1, Bit 6
E3 Frame Number N
E3 Frame Number N + 1
Note: TxOH_Ind pulses high for
16 bit periods in order to
Note:
The FA1 byte will not be processed by
Transmit Paylothaed Data Input
Interface.
denote Overhead Data
Note: TxFrameRefpulses high to denote
(e.g., the FA1 and FA2 bytes)
E3 Frame Boundary.
How to configure the XRT74L73 to operate in this
mode.
1. Set the NibIntf input pin "Low".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "01" as
depicted below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loopback
DS3/E3*
Internal LOS RESET
Enable
Interrupt
Frame Format
Enable Reset
TimRefSel[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
0
1
3. Interface the XRT74L73, to the Terminal Equip-
ment, as illustrated in Figure 166 .
6.2.1.3 Mode 3 - The Serial/Local-Timed/
Frame-Master ModeBehavior of the XRT74L73
If the XRT74L73 has been configured to operate in
this mode, then the XRT74L73 will function as fol-
lows.
A. Local Timed - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT74L73
will use the TxInClk signal as its timing reference.
B. Serial Mode
The XRT74L73 will receive the E3 payload data, in a
serial manner, via the TxSer input pin. The Transmit
Payload Data Input Interface (within the XRT74L73)
will latch this data into its circuitry, on the rising edge
of the TxInClk input clock signal.
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