XRT74L73 Datasheet, PDF (102/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
will set bit-field 2 (TxUT Parity Error Interrupt Status),
within the Transmit UTOPIA Interrupt Enable/Status
Register to “1”, as depicted below.
Transmit UTOPIA Interrupt Enable /Status Register (Address-6Eh)
BIT 7
BIT 6
TxFIFO Reset
Discard Upon
Parity Error
R/W
R/W
x
x
BIT 5
TxUT Parity
Error
Interrupt
Enable
R/W
1
BIT 4
TxFIFO
Overrun Inter-
rupt Enable
R/W
x
BIT 3
TCOCA
Interrupt
Enable
R/W
x
BIT 2
BIT 1
BIT 0
TxUT Parity
Error
Interrupt
Status
TxFIFO
Overrun Inter-
rupt
Status
TCOCA Inter-
rupt
Status
RUR
RUR
RUR
1
x
x
Once the local µP/µC has read the contents of the
Tx UT Interrupt Enable/Status register, then bit 3 of
the UNI Interrupt Status Register, Bit 2 of the TxUT
Interrupt Enable/Status register, and the INTB* output
pin will all be negated, unless outstanding interrupt
conditions are awaiting servicing.
Bit 3—TCOCA Interrupt Enable—Transmit UTOPIA
Change of Cell Alignment Interrupt Enable
This “read/write” bit-field is used for enabling or dis-
abling the “Change of Cell Alignment” interrupt. The
local microprocessor can enable this interrupt by writ-
ing a “1” to this bit-field. Upon power up or reset con-
ditions, this bit-field will contain a “0”. Therefore the
default condition is for this interrupt to be disabled.
TxUT Interrupt Enable/Status Register (Address-6Eh)
BIT 7
BIT 6
Discard Upon
TxFIFO Reset
Parity
Error
R/W
R/W
BIT 5
TxUT Parity
Error
Interrupt
Enable
R/W
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFIFO
Overrun Inter-
rupt Enable
TCOCA Inter-
rupt Enable
TxUT Parity
Error
Interrupt
Status
TxFIFO Over- TCOCA Inter-
run Interrupt
rupt
Status
Status
R/W
R/W
RUR
RUR
RUR
Bit 4—TxFIFO ErrInt Enable—TxFIFO Overrun
Condition Interrupt Enable
This “Read/Write” bit-field is used for enabling or dis-
abling the “TxFIFO Overrun” interrupt. The local mi-
croprocessor can enable this interrupt by writing a “1”
to this bit. Upon power up or reset conditions, this bit
will contain a “0”. Therefore the default condition is for
this interrupt to be disabled. The local microprocessor
must write a “1” to this bit in order to enable this inter-
rupt.
TxUT Interrupt Enable/Status Register (Address-6Eh)
BIT 7
BIT 6
Discard Upon
TxFIFO Reset
Parity
Error
R/W
R/W
BIT 5
TxUT Parity
Error
Interrupt
Enable
R/W
BIT 4
BIT 3
BIT 2
TxFIFO
Overrun Inter-
rupt Enable
TCOCA Inter-
rupt Enable
TxUT Parity
Error
Interrupt
Status
R/W
R/W
RUR
BIT 1
BIT 0
TxFIFO
Overrun Inter-
rupt
Status
TCOCA Inter-
rupt
Status
RUR
RUR
Bit 5—TPerr Interrupt Enable—Detection of Parity
Error in Transmit UTOPIA Block Interrupt Enable
This “Read/Write” bit-field is used for enabling or dis-
abling the “Detected Parity error” interrupt. This inter-
rupt can be enabled by writing a “1” to this bit. Upon
power up or reset conditions, this bit will contain a “0”.
Therefore the default condition is for this interrupt to
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