XRT74L73 Datasheet, PDF (223/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
X
X
X
X
X
X
X
X
The bit-fields of the Tx DS3 M-bit Mask Register, that
are relevant to error-insertion are shaded. The re-
maining bit-fields pertain to the FEBE bit-fields, and
are discussed in Section 4.2.4.2.1.9.
The Tx DS3 M-Bit Mask Register serves two purpos-
es
1. It allows user values to be transmited for FEBE (3
bits) - please see Section 4.2.4.2.1.9.
2. It allows the user to transmit errored P-bits.
3. It allows the user to insert errors into the M-bit
(framing bits) in order to support equipment test-
ing.
Each of these bit-fields are discussed below.
Bit 3 - Tx Err (Transmit Errored) P-Bit
This bit-field allows the user to insert errors into the
P-bits, of each outbound DS3 Frame, for equipment
testing purposes. If this bit-field is 0, then the P-Bits
are transmitted as calculated from the payload of the
previous DS3 frames. However, if this bit-field is 1,
then the P-bits are inverted (from their calculated val-
ue) prior to transmission.
Bits 2 - 0: M-Bit Mask[2:0]
The Transmit DS3 Framer will automatically perform
an XOR operation with the M-bits (in the DS3 data-
stream) and the contents of the corresponding bit-
field, within this register. The results of this operation
will be written back into the M-bit positions within the
outbound DS3 Frames. Therefore, to insure that no
errors are inserted into the M-bits, make sure that the
contents of the M-Bit Mask[2:0] bit-fields are 0.
F-Bit Error Insertion
The remaining mask registers (Tx DS3 F-Bit Mask1
through Mask4 registers) contain bit-fields which cor-
respond to each of the 28 F-bits, within the DS3
frame. Prior to transmission, these bit-fields are auto-
matically XORed with the contents of the correspond-
ing bit fields within these Mask Registers. The result
of this XOR operation is written back into the corre-
sponding bit-field, within the outgoing DS3 frame, and
is transmitted on the line. Therefore, if none of the
bits are to be modified, then these registers must
contain all 0s (the default value).
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36
BIT 7
Unused
RO
0
BIT 6
Unused
RO
0
BIT 5
Unused
RO
0
BIT 4
Unused
RO
0
BIT 3
BIT2
BIT 1
BIT 0
FBit Mask(27) FBit Mask(26) FBit Mask(25) FBit Mask(24)
R/W
R/W
R/W
R/W
0
0
0
0
TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
FBit Mask(23) FBit Mask(22) FBit Mask(21) FBit Mask(20) FBit Mask(19) FBit Mask(18) FBit Mask(17) FBit Mask(16)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
FBit Mask(15) FBit Mask(14) FBit Mask(13) FBit Mask(12) FBit Mask(11) FBit Mask(10) FBit Mask(9) FBit Mask(8)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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