XRT74L73 Datasheet, PDF (27/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
L2 TxPOHFrame_0
L1 TxPOHFrame_1
L4 TxPOHFrame_2
P1
TxNib_3_0/
TxPOHIns_0/
TxHDLCDat_3_0
R3
TxNib_3_1/
TxPOHIns_1/
TxHDLCDat_3_1
R2
TxNib_3_2/
TxPOHIns_2/
TxHDLCDat_3_2
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
O
I
DESCRIPTION
Transmit PLCP Frame Path Overhead Byte Serial Input Port - Beginning of
Frame indicator:
This output pin, along with the TxPOH_n, TxPOHClk_n, and the TxPOHIns_n
pins comprise the "Transmit PLCP Frame POH Byte Insertion" serial input port.
This particular pin will pulse "high" when the "Transmit PLCP POH Byte Inser-
tion" serial input port is expecting the first bit of the Z6 byte at the TxPOH_n input
pin.
NOTE: This pin is only active if the XRT74L73 device has been configured to
operate in the ATM/PLCP Mode.
Transmit Nibble Interface - Bit 3/Transmit PLCP Path Overhead Insert
enable/Transmit HDLC Controller Data Bus - Bit 3 input:
The exact function of this input pin depends upon whether the XRT74L73 device
is configured to operate in the Clear-Channel Framer Mode, the High-Speed
HDLC Controller Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_3_n:
If the user opts to operate the XRT74L73 device in the Nibble-Parallel Mode,
then this input pin will function as the bit 3 (MSB) input to the "Transmit Nibble-
Parallel" input interface. The Transmit Payload Data Input Interface block will
sample this signal (along with TxNib_0_n through TxNib_2_n) upon the falling
edge of TxNibClk_n.
NOTE: This input pin is inactive if the Channel is configured to operate in the
"Serial" Mode.
ATM/PLCP Mode - TxPOHIns_n:
If the XRT74L73 device is configured to operate in the ATM Mode, and if within
the ATM Mode, the chip is also configured to operate in the PLCP Mode, then
this input pin functions as the "Transmit PLCP Path Overhead Port - Enable
input pin". In this mode, the user can externally insert "desired" path overhead
byte values into the "outbound" PLCP frames.The Transmit PLCP Path Over-
head Input port becomes active whenever the user asserts this input pin (by pull-
ing it "high"). Once this occurs, the data, residing upon the "TxPOH_n" input pin
will be sampled upon the rising edge of the "TxPOHClk" signal.
NOTE: This input pin is inactive if the XRT74L73 device is configured to operate
in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_3_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 3"
within this byte wide interface. Data residing on the "Transmit HDLC Controller"
byte wide input interface will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
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