XRT74L73 Datasheet, PDF (295/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
other words, the Transmit Section of the XRT74L73
will initiate frame generation upon the rising edge of
the TxFrameRef input signal).
D. Sampling of payload data, from the Terminal
Equipment
In Mode 2, the XRT74L73 will sample the data, at the
TxSer input pin, on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT74L73 to the Terminal Equip-
ment for Mode 2 Operation
Figure 109 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT74L73) being interfaced to the Terminal Equip-
ment, for Mode 2 operation.
FIGURE 109. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK OF THE XRT74L73 FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION
34.368MHz
Clock Source
E3_Clock_In
E3_Data_Out
Tx_Start_of_Frame
E3_Overhead_Ind
TxInClk
TxSer
TxFrameRef
TxOH_Ind
NibInt
Terminal Equipment
XRT74L73 E3 Framer
Mode 2 Operation of the Terminal Equipment
As shown in Figure 109 , both the Terminal Equip-
ment and the XRT74L73 will be driven by an external
34.368MHz clock signal. The Terminal Equipment
will receive the 34.368MHz clock signal via its
E3_Clock_In input pin, and the XRT74L73 Framer IC
will receive the 34.368MHz clock signal via the TxIn-
Clk input pin.
The Terminal Equipment will serially output the pay-
load data of the outbound E3 data stream, via the
E3_Data_Out output pin, upon the rising edge of the
signal at the E3_Clock_In input pin.
NOTE: The E3_Data_Out output pin of the Terminal Equip-
ment is electrically connected to the TxSer input pin
The XRT74L73 Framer IC will latch the data, residing
on the TxSer input line, on the rising edge of the TxIn-
Clk signal.
In this case, the Terminal Equipment has the respon-
sibility of providing the framing reference signal by
pulsing its Tx_Start_of_Frame output signal (and in
turn, the TxFrameRef input pin of the XRT74L73),
"High" for one-bit period, coincident with the first bit of
a new E3 frame. Once the XRT74L73 detects the ris-
ing edge of the input at its TxFrameRef input pin, it
will begin generation of a new E3 frame.
NOTES:
1. In this case, the Terminal Equipment is controlling
the start of Frame Generation, and is therefore
referred to as the Frame Master. Conversely, since
the XRT74L73 does not control the generation of a
new E3 frame, but is rather driven by the Terminal
Equipment, the XRT74L73 is referred to as the
Frame Slave.
2. If the user opts to configure the XRT74L73 to oper-
ate in Mode 2, it is imperative that the
Tx_Start_of_Frame (or TxFrameRef) signal is syn-
chronized to the TxInClk input clock signal.
Finally, the XRT74L73 will pulse its TxOH_Ind output
pin, one bit-period prior to it processing a given over-
head bit, within the outbound E3 frame. Since the
TxOH_Ind output pin of the XRT74L73 is electrically
connected to the E3_Overhead_Ind whenever the
XRT74L73 pulses the TxOH_Ind output pin "High", it
will also be driving the E3_Overhead_Ind input pin (of
the Terminal Equipment) "High". Whenever the Ter-
minal Equipment detects this pin toggling "High", it
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