XRT74L73 Datasheet, PDF (120/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
2.3.3.4.1Inserting Errors into the B1 Byte
There are occasions when it is desireable to inject er-
rors into the B1 byte of the PLCP frame in order to
verify that the Far-End Receiving hardware is func-
tioning properly and will detect these errors and re-
spond accordingly. The UNI allows the injection these
errors into the B1 byte via the TxPLCP BIP-8 Error
Mask Register, as depicted below.
TxPLCP BIP-8 Error Mask Register, Address = 4Ah
BIT 7
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
BIT 3
B1 Error Mask
R/W
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
R/W
The B1 (BIP-8) byte of a PLCP frame is always XORed
with this mask byte. The results of this operation are
written back into the B1-byte position, prior to trans-
mission. An error can be inserted into a particular bit
of a B1 byte, by writing a “1” into the corresponding bit
in this register.
Note: This register must be 00h for normal operation. This
register is of value 00h following power up or reset.
2.3.3.4.2Inserting Errors into the A1, A2 Bytes
The UNI allows the for the insertion of errors into
each of the “Frame Alignment” bytes A1 and A2.
These errors can be inserted by writing the appropri-
ate data to the “TxPLCP A1 Byte Error Mask Register
(Address = 48h); and the “TxPLCP A2 Byte Error
Mask Register (Address = 49h). The bit formats of
these two registers follows.
TxPLCP A1 Byte Error Mask Register (Address = 48h)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
BIT 3
A1 Error Mask
0
0
BIT 2
0
BIT 1
0
BIT 0
0
TxPLCP A2 Byte Error Mask Register (Address = 49h)
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
BIT 3
A2 Error Mask
0
0
BIT 2
0
BIT 1
0
BIT 0
0
The UNI IC automatically takes each A1 byte from
within an outbound PLCP frame, and performs an
XOR operation with the contents of the “TxPLCP A1
Byte Error Mask” Register. The results of this opera-
tion are written back into the A1 Byte fields of the
PLCP frame, prior to transmission.
The UNI IC also performs the same set of operations
on the A2 bytes of the PLCP frame, with the “TxPLCP
A2 Byte Error Mask” register.
To insure errors are not inserted in the A1 and A2
byte fields of each outbound PLCP frame, these two
registers must contain the value 00h (the default val-
ue).
2.3.3.5Manipulating the FEBE-Nibble Field within
the G1 Bytes
The UNI can either transmit G1 bytes with a FEBE val-
ue of ‘0h’, or to transmit a G1 byte with the correct
FEBE count, as determined by the “Near-End” Re-
ceive PLCP Processor.
This option can be exercised by writing the appropri-
ate data to bit 4 of the TxPLCP G1 Byte Register (Ad-
dress = 4Bh). The bit-format of this register is
presented below.
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