XRT74L73 Datasheet, PDF (101/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
able bits for the Transmit UTOPIA Interface block.
Each of these “interrupt processing relevant” bit fields
are defined below.
Bit 0—TCOCA Interrupt Status—Transmit UTOPIA
Change of Cell Alignment Condition
If the ATM Layer Processor asserts the TxUSoC input
pin prior to writing the contents of a complete cell (as
configured via the CellOf52Bytes option) on the
Transmit UTOPIA Data Bus, then the Transmit UTOPIA
Interface block will interpret this newly received cell
data as a “runt” cell. When the Transmit UTOPIA In-
terface block detects a “runt” cell, it will generate the
“Transmit UTOPIA Change of Cell Alignment Condi-
tion” interrupt, and the “runt” cell will be discarded.
The Transmit UTOPIA Interface Block will indicate
that it is generating this kind of interrupt by asserting
Bit 0 (TCOCA Interrupt Status) within the Transmit
UTOPIA Interrupt Enable/Status Register, as depict-
ed below.
TxUT Interrupt Enable /Status Register (Address-6Eh)
BIT 7
TFIFO
Reset
R/W
x
BIT 6
BIT 5
BIT 4
BIT 3
Discard Upon
Parity Error
TxUT Parity
Error Interrupt
Enable
TxFIFO Over-
run
Interrupt
Enable
TCOCA Inter-
rupt Enable
R/W
R/W
R/W
R/W
x
x
x
1
BIT 2
TxUT Parity
Error
Interrupt
Status
RUR
x
BIT 1
BIT 0
TxFIFO
Overrun Inter-
rupt
Status
TCOCA Inter-
rupt
Status
RUR
RUR
x
1
Bit 1—TxFIFO Overrun Interrupt Status
If the TxFIFO is filled to capacity, and if the ATM Layer
processor attempts to write any additional data to the
TxFIFO, some of the data within the TxFIFO will be
overwritten, and in turn lost. If the Transmit UTOPIA
Interface block detects this condition, and if this
interrupt condition has been enabled then the UNI will
assert the INT* pin to the local µP/µC. Additionally, the
UNI will set bit-field 1, (TxFIFO Overrun Interrupt
Status) within the TxUTOPIA Interrupt Enable/Status
Register to “1”, as depicted below.
Transmit UTOPIA Interrupt Enable /Status Register (Address—6Eh)
BIT 7
TFIFO
Reset
R/W
x
BIT 6
Discard Upon
Parity
Error
R/W
x
BIT 5
BIT 4
BIT 3
BIT 2
TxUT Parity
Error
Interrupt
Enable
TxFIFO Over- TCOCA Inter-
run Interrupt
rupt
Enable
Enable
TxUT Parity
Error
Interrupt
Status
R/W
R/W
R/W
RUR
x
1
x
x
BIT 1
BIT 0
TxFIFO
Overrun Inter-
rupt
Status
TCOCA Inter-
rupt
Status
RUR
RUR
1
x
Bit 1 of the TxUT Interrupt Enable/Status register will
be reset or cleared upon the local µP/µC reading this
register. This action will also negate bit 3 within the
UNI Interrupt Status Register and the INTB* output
pin, unless other outstanding interrupt conditions are
awaiting service.
Bit 2—TPErr Interrupt Status—Detection of Parity
Error via the Transmit UTOPIA Interface Block
The ATM Layer processor is expected to compute and
present the odd-parity value of each byte or word of
ATM Cell data that it intends place on the Transmit
UTOPIA Data bus. As the ATM Layer processor is
writing ATM cell data into the Transmit UTOPIA Inter-
face block, it will place the value of this parity bit at
the TxUPrty input pin of the UNI device while the
corresponding byte (or word) is present on the Transmit
UTOPIA data bus. The Transmit UTOPIA Interface
block will read the contents of the Transmit UTOPIA
Data Bus, and will independently compute the odd-
parity value of that byte or word. Afterwards, the
Transmit UTOPIA Interface block will then compare
its computed parity value with that presented at the
TxUPrty input (by the ATM Layer processor). If these
two parity values are different then a “Transmit UTOPIA
Parity error” has been detected. If this interrupt condition
has been enabled, then the UNI will generate the “De-
tection of Parity Error” interrupt. Additionally, the UNI
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