XRT74L73 Datasheet, PDF (43/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
C3 TxOHENable_0/
TxHDLCDat_7_0
D4 ^{TxOHENable_1/}
TxHDLCDat_7_1
D6
TxOHENable_2/
TxHDLCDat_7_2
AC13
TxMod_0
AC10 TxTSX/TxPSOF
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
I
I
I
DESCRIPTION
Transmit Overhead Enable Output indicator/Transmit HDLC Controller
Data Bit 7 Input:
The function of this input pin depends upon whether the XRT74L73 device is
configured to operate in the "High Speed HDLC Controller Mode or not.
Non-High Speed HDLC Controller Mode - TxOHEnable_n:
The Channel will assert this output pin for one "TxInClk" period just prior to the
instant that the Transmit Overhead Data Input Interface will be sampling and
processing an overhead bit. If the local terminal equipment intends to insert its
own value for an overhead bit into the outbound DS3 or E3 data stream, then it
is expected to sample the state of this signal, upon the falling edge of "TxInClk".
Upon sampling the "TxOHEnable_n" signal high, the local terminal equipment
should (1) place the desired value of the overhead bit, onto the "TxOH_n" input
pin and (2) assert the "TxOHIns_n" input pin. The Transmit Overhead Data
Input Interface block will sample and latch the data on the "TxOH_n" signal,
upon the rising edge of the very next "TxInClk_n" input signal.
High-Speed HDLC Controller Mode - TxHDLCDat_7_n:
If the channel is configured to operate in the High-Speed HDLC Controller mode,
then the local terminal equipment will be provided with a "byte-wide" Transmit
HDLC Controller byte-wide input interface. This input pin will function as "Bit 7"
(the MSB) within this byte wide interface. Data, residing on the "Transmit HDLC
Controller" byte wide input interface, will be sampled upon the rising edge of the
TxHDLCClk_n output signal.
Transmit PPP Data Bus - Modulo Indicator:
This input pin permits the user to specify the number of valid packet octets are
being placed on the TxPData[15:0] input pins.The Link Layer Processor is
expected to set this input pin "low" when both bytes (on the TxPData[15:0] data
bus) is valid packet data. Conversely, the Link Layer Processor is expected to
set this input pin "high" when only the upper octet has valid packet data.
NOTES:
1. This input pin is only active if the XRT74L73 device has been configured
to operate in the PPP Mode.
2. The Link Layer Processor is expected to set this input pin to the appro-
priate state, as each 16-bit word is being written into the TxPData[15:0]
data bus.
Transmit - Start of Transfer/Transmit - Start of PPP Packet (in Chunk
Mode):
The exact function of this input pin depends upon whether the XRT74L73 device
has been configured to operate in the Packet Mode or Cell-Chunk Mode.
Packet Mode - TxTSX
The Link-Layer processor pulses this input pin "high" when an "in-band" port
address is present on the "TxPData[7:0]" bus. When this input pin and
"TxPENB*" are both set "high" then the value of "TxPData[7:0]" is the address
value of the TxFIFO to be selected. Subsequent write operations, into "TxP-
Data[15:0]" will fill the TxFIFO corresponding to this "inband" address.
Chunk Mode - TxPSOF
The Link Layer processor pulses this input pin "high" in order to indicate that the
first byte (or word) of a given Packet is placed on the "TxPData[15:0]" pins.
NOTE: This input pin is only active if the XRT74L73 device has been configured
to operate in the PPP Mode.
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