XRT74L73 Datasheet, PDF (230/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Block Interrupt Enable register (Address = 0x04), as
illustrated below.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Enable
Not Used
R/W
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the Transmit Sec-
tion (at the Block Level) for Interrupt Generation.
Conversely, setting this bit-field to “0” disables the
Transmit Section for interrupt generation.
What does it mean for the Transmit Section Inter-
rupts to be enabled or disabled at the Block Lev-
el?
If the Transmit Section is disabled (for interrupt gen-
eration) at the Block Level, then ALL Transmit Sec-
tion interrupts are disabled, independent of the inter-
rupt enable/disable state of the source level inter-
rupts.
If the Transmit Section is enabled (for interrupt gener-
ation) at the block level, then a given interrupt will be
enabled at the source level. Conversely, if the Trans-
mit Section is enabled (for interrupt generation) at the
Block level, then a given interrupt will still be disabled,
if it is disabled at the source level.
As mentioned earlier, the Transmit Section of the
XRT74L73 Framer IC contains the following two inter-
rupts
• Completion of Transmission of FEAC Message
Interrupt.
• Completion of Transmission of LAPD Message
Interrupt.
The Enabling/Disabling and Servicing of each of
these interrupts is described below.
4.2.6.1.1 The Completion of Transmission of
FEAC Message Interrupt.
If the Transmit Section interrupts have been enabled
at the Block level, then the Completion of Transmis-
sion of a FEAC Message Interrupt can be enabled or
disabled by writing the appropriate value into Bit 4 (Tx
FEAC Interrupt Enable) within the Transmit DS3
FEAC Configuration & Status Register (Address =
0x31) as illustrated below.
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Not Used
Tx FEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
GO
RO
RO
RO
R/W
RUR
R/W
R/W
0
0
0
X
0
0
0
BIT 0
TxFEAC
Busy
RO
0
Setting this bit-field to “1” enables the Completion of
Transmission of a FEAC Message Interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
4.2.6.1.2 Servicing the Completion of Trans-
mission of a FEAC Message Interrupt
As mentioned earlier, once the user commands the
Transmit FEAC Processor to begin its transmission of
a FEAC Message, it will do the following.
1. It will read in the six-bit contents of the Tx DS3
FEAC Register (Address = 0x32) and encapsu-
late these 6 bits into a 16-bit data structure.
2. The Transmit FEAC Processor will then begin to
transmit this 16-bit data structure (to the Remote
Terminal Equipment) repeatedly for 10 consecu-
tive times.
3. Upon completion of the 10th transmission, the
XRT74L73 Framer IC will generate the Comple-
tion of Transmission of a FEAC Message Inter-
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