XRT74L73 Datasheet, PDF (34/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
W24
W25
W26
NAME
RxLCD_0/
RxOutClk_0/
RxHDLCDat_7_0
RxLCD_1/
RxOutClk_1/
RxHDLCDat_7_1
RxLCD_2/
RxOutClk_2/
RxHDLCDat_7_2
TYPE
O
DESCRIPTION
Receive Loss of Cell Delineation indicator/Receive Output Clock signal/
Receive HDLC Controller Data Bus - Bit 7 Output:
The exact function of output pin depends upon whether the channel has been
configured to operate in the ATM, Clear-Channel Framer or High Speed HDLC
Controller Mode.
ATM Mode - RxLCD_n:
This active-high output pin will be asserted whenever the Receive Cell Proces-
sor has experienced a "Loss of Cell Delineation". This pin will return "low" once
the Receive Cell Processor has regained Cell Delineation.
Clear-Channel Framer Mode - RxOutClk_n:
This clock signal functions as the Transmit Payload Data Input Interface clock
source, if the channel has been configured to operate in the "local-timing"
mode.In this mode, the local terminal equipment is expected to input data to the
TxSer_n input pin, upon the rising edge of this clock signal. The channel will use
the rising edge of this signal to sample the data on the TxSer_n input.
High-Speed HDLC Controller Mode - RxHDLCDat_7_n:
This output pin, along with RxHDLCDat_[6:0]_n function as the Receive HDLC
Controller byte wide output data bus. This particular output pin functions ass the
MSB (Most Significant Bit) of the Receive HDLC Controller byte wide data bus.
The Receive HDLC Controller will output the contents of all HDLC frames via
this output data bus, upon the rising edge of the "RxHDLCClk_n" output signal.
Hence, the user’s local terminal equipment should be designed/configured to
sample this data upon the falling edge of the "RxHDLCClk_n" output clock sig-
nal.
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