XRT74L73 Datasheet, PDF (348/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
RO
RO
RO
RUR
RUR
0
0
0
0
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
1
• Assert the RxAIS output pin.
• Set Bit 3 (RxAIS) within the Rx E3 Configuration &
Status Register, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
R/W
RO
RO
RO
RO
RO
RO
0
1
1
0
1
1
1
BIT 0
RxFERF
RO
1
Clearing the AIS Condition
The Receive E3 Framer block will clear the AIS con-
dition when it detects two consecutive E3 frames,
with eight or more “zeros” in the incoming data
stream. The Receive E3 Framer block will inform the
Microprocessor that the AIS Condition has been
cleared by:
• Generating the Change in AIS Condition Interrupt
to the Microprocessor. Hence, the Receive E3
Framer block will assert Bit 0 (AIS Interrupt Status)
within the Rx E3 Framer Interrupt Status Register -
1.
• Clearing the RxAIS output pin (e.g., toggling it
"Low”).
• Setting the RxAIS bit-field, within the Rx E3 Config-
uration & Status Register to “0”, as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
1
0
0
X
5.3.2.9 The Far-End-Receive Failure (FERF)
Condition
Declaring the FERF Condition
The Receive E3 Framer block will declare a Far-End
Receive Failure (FERF) condition if it detects a user-
selectable number of consecutive incoming E3
frames, with the “A” bit-field set to “1”.
This User-selectable number of E3 frames is either 3
or 5, depending upon the value that has been written
into Bit 4 (RxFERF Algo) within the Rx E3 Configura-
tion & Status Register, as depicted below.
349