XRT74L73 Datasheet, PDF (158/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FIGURE 36. FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE UTOPIA INTERFACE BLOCK
Read
Write
A[8:0]
D[15:0]
From RxCP
RxFData[7:0]
RxFWrClk
RWrEn
RxUSoC
Controls from
Registers
RxUClk
RxUEn
RxUAddr [4:0]
RxUData [15:0]
RxUData [7:0]
RxUtopia
Registers
Control Signals
Status Signals
Rx Utopia
Cell FIFO
RxUData [7:0]/
RxUData [15:0]
RxUSoC
To Pins
Status Bits to Registers
RxUClav
(To Pin)
RxUPrty
RxUtopia Interrupt (To Interrupt block)
The following sections discuss each functional sub-
block of the Receive UTOPIA Interface block in detail.
Additionally, these sections discuss many of the fea-
tures associated with the Receive UTOPIA Interface
block as well as how these features can be optimized
to suit selected application needs. Detailed discus-
sion of Single-PHY and Multi-PHY operation will be
presented in its own section even though it involves
the use of all of these functional blocks.
3.4.2.1Receive UTOPIA Bus Output Interface
The Receive UTOPIA output interface complies with
the UTOPIA Level 2 standard interface (e.g., the
Receive UTOPIA can support both Single-PHY and
Multi-PHY operations). Additionally, the UNI provides
the option of varying the following features associated
with the Receive UTOPIA Bus interface.
• Receive UTOPIA Data Bus width of 8 or 16 bits.
• The cell size (e.g., the number of octets being processed
per cell via the UTOPIA bus)
A discussion of the operation of the Receive UTOPIA
Bus Interface along with each of these options will be
presented below.
3.4.2.1.1The Pins of the Receive UTOPIA Bus
Interface
The ATM Layer processor will interface to the Receive
UTOPIA Interface block via the following pins.
• RxUData[15:0]—Receive UTOPIA Data Bus output
pins.
• RxUAddr[4:0]—Receive UTOPIA Address Bus
input pins.
• RxUClk—Receive UTOPIA Interface Block clock
input pin.
• RxUSoC—Receive “Start of Cell” Indicator output
pin.
• RxUPrty—Receive UTOPIA—Odd Parity output
pin.
• RxUEn—Receive UTOPIA Data Bus—Output
Enable input pin.
• RxUClav/RxFullB*—RxFIFO Cell Available output
pin.
Each of these signals are discussed below.
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