XRT74L73 Datasheet, PDF (285/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
message) in 3 of the last 10 FEAC Message recep-
tions.
Enabling/Disabling the Receive FEAC Message -
Removal Interrupt
To enable or disable the Receive FEAC Message -
Removal Interrupt, write the appropriate data into Bit
3 (RxFEAC Remove Interrupt Enable) within the
RxDS3 FEAC Interrupt Enable/Status Register, as in-
dicated below.
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
Not Used
BIT 5
BIT 4
FEAC Valid
BIT 3
RxFEAC
Remove
Interrupt
Enable
BIT 2
RxFEAC
Remove
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
0
0
0
0
X
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
X
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the Receive FEAC Message - Validation
Interrupt.
Whenever the XRT74L73 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "Low".
• It will set Bit 2 (RxFEAC Remove Interrupt Status),
within the RxDS3 FEAC Interrupt Enable/Status
Register to “1”, as indicated below.
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
R/W
RUR
0
0
0
0
0
0
1
1
• It will write the delete contents of the most recently
validated FEAC Message from the Rx DS3 FEAC
Register, as indicated below.
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
RxFEAC[5:0]
RO
RO
RO
RO
R/O
0
X
X
X
X
BIT 2
R/O
X
BIT 1
R/O
X
BIT 0
Not Used
R/O
0
4.3.6.2.11 The Completion of Reception of a
LAPD Message Interrupt
If the Completion of Reception of a LAPD Message
interrupt is enabled, then the XRT74L73 Framer IC
will generate an interrupt anytime the Receive HDLC
Controller block has received a new LAPD Message
buffer, from the Remote Terminal Equipment, and has
286