XRT74L73 Datasheet, PDF (396/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
6.2.1.5 Mode 5 - The Nibble-Parallel/Local-
Time/Frame-Slave Interface Mode Behavior of the
XRT74L73
If the XRT74L73 has been configured to operate in
this mode, then the XRT74L73 will function as fol-
lows:
A. Local Timing - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT74L73
will use the TxInClk signal at its timing reference.
Further, the chip will internally divide the TxInClk
clock signal by a factor of 4 and will output this divid-
ed clock signal via the TxNibClk output pin. The
Transmit Terminal Equipment Input Interface block
(within the XRT74L73) will use the rising edge of the
TxNibClk signal, to latch the data, residing on the Tx-
Nib[2:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT74L73 will accept the DS3 payload data,
from the Terminal Equipment, in a parallel manner,
via the TxNib[2:0] input pins. The Transmit Terminal
Equipment Input Interface will latch this data into its
circuitry, on the rising edge of the TxNibClk output
signal.
C. Delineation of Outbound E3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will use the TxFrameRef
input signal as its Framing Reference (e.g., the
Transmit Section of the XRT74L73 initiates frame
generation upon the rising edge of the TxFrameRef
signal).
D. Sampling of payload data, from the Terminal
Equipment
In Mode 5, the XRT74L73 will sample the data, at the
TxNib[2:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNib-
Clk signal (see Figure 173 ).
NOTE: The TxNibClk signal, from the XRT74L73 operates
nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT74L73 to the Terminal Equip-
ment for Mode 5 Operation
Figure 172 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT74L73) being interfaced to the Terminal Equip-
ment, for Mode 5 Operation.
FIGURE 172. THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK OF THE XRT74L73 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIME/FRAME-SLAVE) OPERATION
E3_Nib_Clock_In
E3_Data_Out[2:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz
Clock Source
8.592MHz
4
TxInClk
TxNibClk
NibInt
TxNib[2:0]
TxFrameRef
TxOH_Ind
VCC
Terminal Equipment
XRT74L73 E3 Framer
Mode 5 Operation of the Terminal Equipment
In Figure 172 both the Terminal Equipment and the
XRT74L73 will be driven by an external 8.592MHz
clock signal. The Terminal Equipment will receive the
8.592MHz clock signal via the E3_Nib_Clock_In input
pin. The XRT74L73 will output the 8.592MHz clock
signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the E3_Data_Out[2:0] pins, upon the rising edge
of the signal at the E3_Clock_In input pin.
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