XRT74L73 Datasheet, PDF (32/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
AF8
AE9
AF9
NAME
TxNibClk_0/
TxGFCMSB_0/
SendFCS_0
TxNibClk_1/
TxGFCMSB_1/
SendFCS_1
TxNibClk_2/
TxGFCMSB_2/
SendFCS_2
TYPE
O
DESCRIPTION
Transmit Nibble Clock Output pin/Transmit GFC Byte - MSB Indicator Out-
put/Send FCS Value Request Input:
The exact function of this input/output pin depends upon whether the XRT74L73
device is configured to operate in the Clear-Channel Framer Mode, the High-
Speed HDLC Controller Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNibClk_n
If the user opts to operate the XRT74L73 device in the Nibble-Parallel Mode,
then the XRT74L73 device will derive this clock signal from either the "TxInClk"
or the "RxLineClk" signal (depending upon whether the chip is operating in the
"Local-Timing" or "Loop-Timing" Mode).
The user is advised to configure the Terminal Equipment to output the "out-
bound" payload data (to the XRT74L73 device) onto the "TxNib_[2:0]_n" input
pins, upon the rising edge of this clock signal. The Transmit Payload Data Input
Interface block will sample the data, residing on the "TxNib_[2:0]_n line, upon
the falling edge this clock signal.
NOTES:
1. For DS3 applications, the XRT74L73 device will output 1176 clock
pulses (to the local terminal equipment) for each "outbound" DS3 frame.
2. For E3, ITU-T G.832 applications, the XRT74L73 device will output 1074
clock pulses (to the local terminal equipment) for each "outbound" E3
frame.
3. For E3, ITU-T G.751 applications, the XRT74L73 device will output 384
clock pulses (to the local terminal equipment) for each "outbound" E3
frame.
ATM Mode - TxGFCMSB_n:
This signal, along with TxGFC and TxGFCClk combine to function as the "Trans-
mit GFC Nibble Field" serial input port. This output signal will pulse "high" when
the MSB (most significant bit) of the GFC nibble (for a given "outbound" cell) is
expected at the TxGFC_n input pin.
High-Speed HDLC Controller Mode - SendFCS_n:
The local terminal equipment is expected to control both this input pin along with
the SendMSG input pin during the construction and transmission of each out-
bound HDLC frame.This input pin permits the user to command the Transmit
HDLC Controller block to compute and insert the computed FCS (Frame-Check
Sequence) value into the back-end of the outbound HDLC frame as a trailer.If
the user has configured the Transmit HDLC Controller block to compute and
insert a CRC-16 value into the outbound HDLC frame, then the local terminal
equipment is expected to hold this input pin "high" for two periods of
"TxHDLCClk_n". Conversely, if the user has configured the Transmit HDLC Con-
troller block to compute and insert a CRC-32 value into the outbound HDLC
frame, then the local terminal equipment is expected to hold this input pin "high"
for four (4) periods of "TxHDLCClk_n".
NOTES:
1. This input/output pin is inactive if the XRT74L73 device has been config-
ured to operate in the PPP Mode.
2. This input/output pin is inactive if the XRT74L73 device has been config-
ured to operate in the "Clear-Channel Framer/Serial mode".
33