XRT74L73 Datasheet, PDF (157/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
• Inform the ATM Layer Processor whenever the
RxFIFO contains cell data that needs to be read.
• Inform the ATM Layer Processor that it has no more
cell data to be read.
• Compute and present the odd-parity value of the
byte (or word) that is present at the Receive UTOPIA
Data Bus.
• Indicate the boundaries of cells, to the ATM Layer pro-
cessor, by pulsing the RxUSoC (Receive Start of Cell)
pin each time the first byte (or word) of a new cell is
present on the Receive UTOPIA Data Bus.
The Receive UTOPIA Interface Block consists of the
following sub-blocks:
• Receive UTOPIA Output Interface
• Receive UTOPIA Cell FIFO (RxFIFO)
• Receive UTOPIA FIFO Manager
The Receive UTOPIA Interface block consists of an
output interface complying to the “UTOPIA Level 2
Interface Specifications”, and the RxFIFO. The width
of the Receive UTOPIA Data Bus is User-configurable
to be either 8 or 16 bits. The Receive UTOPIA Inter-
face block also allows the ATM Layer processor to
perform parity checking on all data that it receives
from it (the Receive UTOPIA Interface block), over
the Receive UTOPIA Data bus. The Receive UTOPIA
Interface block computes the odd-parity of each byte
(or word) that it will place on the Receive UTOPIA
data bus. The Receive UTOPIA Interface block will
then output the value of this computed parity at the
RxUPrty pin, while the corresponding data byte
(word) is present at the RxUData[15:0] output pins.
The Receive UTOPIA Interface block can be config-
ured to process 52, 53, and 54 bytes per cell; and will
assert the RxUSoC (Receive “Start of Cell”) output
pin at the cell boundaries. If the Receive UTOPIA In-
terface block detects a “runt” cell (e.g., a cell that is
smaller than what the Receive UTOPIA Interface
block has been configured to handle), it will generate
an interrupt to the local µP, discard this “runt” cell, and
resume normal operation.
The physical size of the RxFIFO is four cells. The
incoming data (from the Receive Cell Processor) is
written into the RxFIFO, where it can be read in and
processed by the ATM Layer Processor. A FIFO Man-
ager maintains the RxFIFO and indicates the FIFO
Empty and FIFO Full to the local µP. Additionally the
FIFO Manager will indicate that ATM Cell Data is
available in the RxFIFO, by asserting the RxUClav out-
put pin. Figure 36 presents a Functional Block Diagram
of the Receive UTOPIA Interface Block.
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