XRT74L73 Datasheet, PDF (145/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TABLE 25: ILLUSTRATION OF THE ROLE OF THE “RXCP IDLE CELL PATTERN HEADER BYTE” REGISTER, AND THE
“RXCP IDLE CELL MASK HEADER BYTE” REGISTER (CONTINUED)
Comments
BIT 7
BIT 6
BIT 5
BIT 4
Comparison is Forced (by the “1s” in the RxCP Idle Cell Mask
Header Byte-1 Register)
BIT 3
Don’t Care
BIT 2
Don’t Care
BIT 1
Don’t Care
BIT 0
Don’t Care
Results of Comparison
BIT 7
BIT 6
1
0
BIT 5
1
BIT 4
0
BIT 3
x
BIT 2
x
BIT 1
x
BIT 0
x
Based upon these register settings, any cell containing
values in the range of A0h–AFh are considered to be
matching the “Idle Cell Pattern”, at the first byte. This
incoming cell will be subjected to three (3) more tests
(e.g., one for each of the remaining header bytes) be-
fore it is identified as an Idle Cell or not.
Consequently, if the user opts to “discard” Idle Cells,
then any cells, passing the above-described tests,
will be identified as an Idle Cell and will be discarded
by the Receive Cell Processor.
The bit format for each of these eight “Idle Cell” iden-
tification registers are listed below.
RxCP Idle Cell Pattern Header Byte-1 Register (Address = 50h)
BIT 7
R/W
0
BIT 6
R/W
0
BIT 5
R/W
0
BIT 4
BIT 3
RxIdle Cell Pattern—Header Byte 1
R/W
R/W
0
0
BIT 2
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
RxCP Idle Cell Pattern Header Byte-2 Register (Address = 51h)
BIT 7
R/W
0
BIT 6
R/W
0
BIT 5
R/W
0
BIT 4
BIT 3
RxIdle Cell Pattern—Header Byte 2
R/W
R/W
0
0
BIT 2
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
RxCP Idle Cell Pattern Header Byte-3 Register (Address = 52h)
BIT 7
R/W
0
BIT 6
R/W
0
BIT 5
R/W
0
BIT 4
BIT 3
RxIdle Cell Pattern—Header Byte 3
R/W
R/W
0
0
BIT 2
R/W
0
BIT 1
R/W
0
BIT 0
R/W
0
RxCP Idle Cell Pattern Header Byte-4 Register (Address = 53h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxIdle Cell Pattern—Header Byte
BIT 2
BIT 1
BIT 0
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