DS083 Datasheet, PDF (93/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 32: IOB Input Switching Characteristics (Continued)
Speed Grade
Description
Symbol
Device
-7
-6
-5
Setup and Hold Times With Respect to
Clock at IOB Input Register
Pad, no delay
Pad, with delay
T_IOPICK/T_IOICKP
T_IOPICKD/T_IOICKPD
All
XC2VP2
XC2VP4
0.84/–0.61
2.28/–1.89
2.55/–2.10
0.86/–0.63
2.60/–2.15
2.87/–2.36
0.90/–0.67
2.95/–2.43
3.21/–2.65
XC2VP7 2.48/–2.05 2.82/–2.32 3.15/–2.60
XC2VP20 2.63/–2.05 3.02/–2.35 3.40/–2.66
XC2VPX20 2.63/–2.05 3.02/–2.35 3.40/–2.66
XC2VP30 2.67/–2.07 3.09/–2.42 3.49/–2.73
XC2VP40 3.28/–2.56 3.61/–2.83 4.01/–3.15
XC2VP50 3.84/–3.02 4.08/–3.21 4.42/–3.48
XC2VP70 3.98/–3.13 4.23/–3.33 4.55/–3.58
XC2VPX70 3.98/–3.13 4.23/–3.33 4.55/–3.58
XC2VP100
N/A
6.48/–5.13 7.04/–5.57
ICE input
SR input (IFF, synchronous)
Set/Reset Delays
T_IOICECK/T_IOCKICE
All
T_IOSRCKI
All
0.39/ 0.01
0.52
0.44/ 0.01
0.57
0.49/ 0.01
0.75
SR input to IQ (asynchronous)
T_IOSRIQ
All
1.13
1.27
1.42
GSR to output IQ
T_GSRQ
All
5.87
6.75
7.43
Notes:
1. Input timing for LVCMOS25 is measured at 1.25V. For other I/O standards, see Table 36.
Units
ns, min
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, max
ns, max
DS083 (v4.7) November 5, 2007
Product Specification
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