DS083 Datasheet, PDF (57/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Each block SelectRAM+ cell is a fully synchronous memory,
as illustrated in Figure 48. The two ports have independent
inputs and outputs and are independently clocked.
18-Kbit Block SelectRAM
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DOA
DOPA
ing or falling clock edge causes the data to be loaded into
the memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. WRITE_FIRST
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO,
as shown in Figure 49.
DIB
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
DOB
DOPB
DS031_11_102000
Figure 48: 18 Kb Block SelectRAM+ in Dual-Port Mode
Port Aspect Ratios
Table 23 shows the depth and the width aspect ratios for the
18 Kb block SelectRAM+ resource. Virtex-II Pro block
SelectRAM+ also includes dedicated routing resources to
provide an efficient interface with CLBs, block SelectRAM+,
and multipliers.
Table 23: 18 Kb Block SelectRAM+ Port Aspect Ratio
Width Depth Address Bus Data Bus Parity Bus
1
16,384 ADDR[13:0]
DATA[0]
N/A
2
8,192 ADDR[12:0] DATA[1:0]
N/A
4
4,096 ADDR[11:0] DATA[3:0]
N/A
9
2,048 ADDR[10:0] DATA[7:0] Parity[0]
18
1,024
ADDR[9:0] DATA[15:0] Parity[1:0]
36
512
ADDR[8:0] DATA[31:0] Parity[3:0]
Read/Write Operations
The Virtex-II Pro block SelectRAM+ read operation is fully
synchronous. An address is presented, and the read opera-
tion is enabled by control signal ENA or ENB. Then,
depending on clock polarity, a rising or falling clock edge
causes the stored data to be loaded into output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA and WEB in addition to ENA or
ENB. Then, again depending on the clock input mode, a ris-
Data_in
Internal
DI _Memory
DO
Data_out = Data_in
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
New
DS083-2_14_050901
Figure 49: WRITE_FIRST Mode
2. READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in
Figure 50.
Data_in
Internal
DI _Memory
DO
Prior stored data
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
Old
DS083-2_13_050901
Figure 50: READ_FIRST Mode
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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