DS083 Datasheet, PDF (16/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
RXP and RXN as shown in Figure 5. This supports multiple
termination styles, including high-side, low-side, and differ-
ential (floating or active). This configuration supports
receiver termination compatible to Virtex-II Pro devices,
using a CML (high-side) termination to an active supply of
1.8V – 2.5V. For DC coupling of two Virtex-II Pro X devices,
a 1.5V CML termination for VTRX is recommended.
VTRX
50Ω
50Ω
RXP
RXN
ds083-2_35_050704
Figure 5: RocketIO X Receive Termination
PCS
Fabric Data Interface
Internally, the PCS operates in either 2-byte mode (16/20
bits) or 4-byte mode (32/40 bits). When in 2-byte mode, the
FPGA fabric interface can either be 1, 2, or 4 bytes wide.
When in 4-byte mode, the FPGA fabric interface can either
be 4 or 8 bytes wide. When accompanied by the predefined
modes of the PMA, the user thus has a large combination of
protocols and data rates from which to choose.
USRCLK2 clocks data on the fabric side, while USRCLK
clocks data on the PCS side. This creates distinct USR-
CLK/USRCLK2 frequency ratios for different combinations
of fabric and internal data widths. Table 2 summarizes the
USRCLK2-to-USRCLK ratios for the different possible com-
binations of data widths.
Table 2: Clock Ratios for Various Data Widths
Frequency Ratio of USRCLK:USRCLK2
Fabric
Data Width
1 byte
2-Byte Internal
Data Width
1:2 ⁽¹⁾
4-Byte Internal
Data Width
N/A
2 byte
4 byte
8 byte
1:1
2:1 ⁽¹⁾
N/A
N/A
1:1
2:1⁽¹⁾
Notes:
1. Each edge of slower clock must align with falling edge of faster clock.
As a general guide, use 2-byte internal data width mode
when the serial speed is below 5 Gb/s, and 4-byte internal
data width mode when the serial speed is greater than
5 Gb/s. In 2-byte mode, the PCS processes 4-byte data
every other byte.
No fixed phase relationship is assumed between REFCLK,
RXRECCLK, and/or any other clock that is not tied to either
of these clocks. When RXUSRCLK and RXUSRCLK2 have
different frequencies, each edge of the slower clock is
aligned to a falling edge of the faster clock. The same rela-
tionships apply to TXUSRCLK and TXUSRCLK2.
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of
data to the transmitter. Each character can be either 8 bits
or 10 bits wide. If 8-bit data is applied, the additional inputs
become control signals for the 8B/10B encoder. When the
8B/10B encoder is bypassed, the 10-bit character order is
generated as follows:
TXCHARDISPMODE[0]
(first bit transmitted)
TXCHARDISPVAL[0]
TXDATA[7:0] (last bit transmitted is TXDATA[0])
64B/66B Encoder/Decoder
The RocketIO X PCS features a 64B/66B encoder/decoder,
scrambler/descrambler, and gearbox functions that can be
bypassed as needed. The encoder is compliant with IEEE
802.3ae specifications.
Scrambler/Gearbox
The bypassable scrambler operates on the read side of the
transmit FIFO. The scrambler uses the following generator
polynomial to scramble 64B/66B payload data:
G(x) = 1 + x³⁹ + x⁵⁸
The scrambler works in conjunction with the gearbox, which
frames 64B/66B data for the PMA. The gearbox should
always be enabled when using the 64B/66B protocal.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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