DS083 Datasheet, PDF (106/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table 43: Pipelined Multiplier Switching Characteristics
Description
Setup and Hold Times Before/After Clock
Data Inputs
Clock Enable
Reset
Clock to Output Pin
Clock to Pin35
Clock to Pin34
Clock to Pin33
Clock to Pin32
Clock to Pin31
Clock to Pin30
Clock to Pin29
Clock to Pin28
Clock to Pin27
Clock to Pin26
Clock to Pin25
Clock to Pin24
Clock to Pin23
Clock to Pin22
Clock to Pin21
Clock to Pin20
Clock to Pin19
Clock to Pin18
Clock to Pin17
Clock to Pin16
Clock to Pin15
Clock to Pin14
Clock to Pin13
Clock to Pin12
Clock to Pin11
Clock to Pin10
Clock to Pin9
Clock to Pin8
Clock to Pin7
Clock to Pin6
Clock to Pin5
Clock to Pin4
Clock to Pin3
Clock to Pin2
Clock to Pin1
Clock to Pin0
Symbol
T_MULIDCK/T_MULCKID
T_{MULIDCK_CE}/T_{MULCKID_CE}
T_{MULIDCK_RST}/T_{MULCKID_RST}
T_{MULTCK_P35}
T_{MULTCK_P34}
T_{MULTCK_P33}
T_{MULTCK_P32}
T_{MULTCK_P31}
T_{MULTCK_P30}
T_{MULTCK_P29}
T_{MULTCK_P28}
T_{MULTCK_P27}
T_{MULTCK_P26}
T_{MULTCK_P25}
T_{MULTCK_P24}
T_{MULTCK_P23}
T_{MULTCK_P22}
T_{MULTCK_P21}
T_{MULTCK_P20}
T_{MULTCK_P19}
T_{MULTCK_P18}
T_{MULTCK_P17}
T_{MULTCK_P16}
T_{MULTCK_P15}
T_{MULTCK_P14}
T_{MULTCK_P13}
T_{MULTCK_P12}
T_{MULTCK_P11}
T_{MULTCK_P10}
T_{MULTCK_P9}
T_{MULTCK_P8}
T_{MULTCK_P7}
T_{MULTCK_P6}
T_{MULTCK_P5}
T_{MULTCK_P4}
T_{MULTCK_P3}
T_{MULTCK_P2}
T_{MULTCK_P1}
T_{MULTCK_P0}
Speed Grade
-7
-6
-5
Units
1.86/ 0.00
0.23/ 0.00
0.21/–0.09
2.06/ 0.00
0.25/ 0.00
0.24/–0.09
2.31/ 0.00
0.28/ 0.00
0.26/–0.10
ns, max
ns, max
ns, max
2.45
2.92
3.27
ns, max
2.36
2.82
3.16
ns, max
2.28
2.72
3.05
ns, max
2.20
2.62
2.93
ns, max
2.12
2.52
2.82
ns, max
2.03
2.42
2.71
ns, max
1.95
2.32
2.60
ns, max
1.87
2.22
2.48
ns, max
1.79
2.12
2.37
ns, max
1.70
2.02
2.26
ns, max
1.62
1.92
2.15
ns, max
1.54
1.82
2.03
ns, max
1.46
1.71
1.92
ns, max
1.37
1.61
1.81
ns, max
1.29
1.51
1.69
ns, max
1.21
1.41
1.58
ns, max
1.13
1.31
1.47
ns, max
1.04
1.21
1.36
ns, max
0.96
1.11
1.24
ns, max
0.88
1.01
1.13
ns, max
0.80
0.91
1.02
ns, max
0.71
0.81
0.91
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
0.63
0.71
0.79
ns, max
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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