DS083 Datasheet, PDF (144/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FG456/FGG456 Fine-Pitch BGA Package
As shown in Table 6, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FG456/FGG456 fine-pitch
BGA package. The pins in these devices are same, except for the differences shown in the "No Connects" column. Following
this table are the FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0/VREF_0
IO_L05_0/No_Pair
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0
IO_L09P_0/VREF_0
IO_L67N_0
IO_L67P_0
IO_L69N_0
IO_L69P_0/VREF_0
IO_L74N_0/GCLK7P
IO_L74P_0/GCLK6S
IO_L75N_0/GCLK5P
IO_L75P_0/GCLK4S
Pin Number
D5
D6
E6
E7
D7
C7
E8
D8
C8
F9
E9
D9
D10
F10
E10
C10
B11
F11
E11
D11
C11
No Connects
XC2VP2 XC2VP4 XC2VP7
1
IO_L75N_1/GCLK3P
C12
1
IO_L75P_1/GCLK2S
D12
1
IO_L74N_1/GCLK1P
E12
1
IO_L74P_1/GCLK0S
F12
1
IO_L69N_1/VREF_1
B12
1
IO_L69P_1
C13
1
IO_L67N_1
E13
1
IO_L67P_1
F13
1
IO_L09N_1/VREF_1
D13
1
IO_L09P_1
D14
1
IO_L07N_1
E14
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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