DS083 Datasheet, PDF (133/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 4: Virtex-II Pro Pin Definitions (Continued)
Pin Name
Direction
Description
GCLKx (S/P)
Input/Output
These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
These pins can be used to clock the RocketIO transceiver. See the RocketIO
Transceiver User Guide for design guidelines and BREFCLK-specific pins, by device.
VRP
Input
This pin is for the DCI voltage reference resistor of P transistor (per bank).
VRN
Input
This pin is for the DCI voltage reference resistor of N transistor (per bank).
V_REF
Dedicated Pins:⁽¹⁾
Input
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
CCLK
Input/Output Configuration clock. Output in Master mode or Input in Slave mode.
PROG_B
Input
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE
Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0
Input
Configuration mode selection. Pin is biased by V_CCAUX (must be 2.5V). These pins
should not connect to 3.3V unless 100Ω series resistors are used. The mode pins are
not to be toggled (changed) while in operation during and after configuration.
HSWAP_EN
Input
Enable I/O pull-ups during configuration.
TCK
Input
Boundary Scan Clock. This pin is 3.3V compatible.
TDI
Input
Boundary Scan Data Input. This pin is 3.3V compatible.
TDO
Output Boundary Scan Data Output. Pin is open-drain and can be pulled up to 3.3V. It is
(open-drain) recommended that the external pull-up be greater than 200Ω. There is no internal
pull-up.
TMS
Input
Boundary Scan Mode Select. This pin is 3.3V compatible.
PWRDWN_B
Input
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
(unsupported) device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Other Pins:
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
V_BATT
Input
Decryptor key memory backup supply. (Connect to V_CCAUX or GND if battery not
used.)
RSVD
N/A
Reserved pin - do not connect.
V_CCO
V_CCAUX
V_CCINT
GND
Input
Input
Input
Input
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
AVCCAUXRX#
Input
Analog power supply for receive circuitry of the RocketIO MGT (2.5V).
AVCCAUXTX#
Input
Analog power supply for transmit circuitry of the RocketIO MGT (2.5V).
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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