DS083 Datasheet, PDF (104/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Table 40: CLB Distributed RAM Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
T_SHCKO16
T_SHCKO32
T_SHCKOF5
1.25
1.57
1.52
1.38
1.75
1.68
1.54
ns, max
1.95
ns, max
1.88
ns, max
BX/BY data inputs (DIN)
F/G address inputs
SR input
Clock CLK
T_DS/T_DH
T_AS/T_AH
T_WES/T_WEH
0.38/–0.07
0.42/ 0.00
0.22/ 0.04
0.41/–0.07
0.47/ 0.00
0.24/ 0.05
0.46/–0.08
0.52/ 0.00
0.26/ 0.05
ns, min
ns, min
ns, min
Minimum Pulse Width, High
T_WPH
0.63
0.72
0.79
ns, min
Minimum Pulse Width, Low
T_WPL
0.63
0.72
0.79
ns, min
Minimum clock period to meet address write cycle time
T_WC
1.25
1.44
1.58
ns, min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if
a “0” is listed, there is no positive hold time.
CLB Shift Register Switching Characteristics
Table 41: CLB Shift Register Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Units
Sequential Delays
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
T_REG
T_REG32
T_REGXB
T_REGYB
T_CKSH
T_REGF5
2.78
3.12
3.49
ns, max
3.10
3.49
3.90
ns, max
2.84
3.18
3.55
ns, max
2.55
2.88
3.21
ns, max
2.50
2.83
3.15
ns, max
3.05
3.42
3.83
ns, max
BX/BY data inputs (DIN)
SR input
Clock CLK
T_SRLDS/T_SRLDH 0.70/–0.16 0.77/–0.18 0.98/–0.21
T_WSS/T_WSH 0.27/ 0.01 0.34/ 0.01 0.47/ 0.01
ns, min
ns, min
Minimum Pulse Width, High
T_SRPH
0.63
0.72
0.79
ns, min
Minimum Pulse Width, Low
T_SRPL
0.63
0.72
0.79
ns, min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if
a “0” is listed, there is no positive hold time.
DS083 (v4.7) November 5, 2007
Product Specification
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