DS083 Datasheet, PDF (12/430 Pages) Xilinx, Inc – Summary of Features

6
R 0 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Functional Description
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro⁽¹⁾ Array Functional Description
DCM
RocketIO or RocketIO X
Multi-Gigabit Transceiver
CLB
CLB
CLB
CLB
Configurable
Logic
SelectIO-Ultra
DS083-1_01_050304
Figure 1: Virtex-II Pro Generic Architecture Overview
This module describes the following Virtex™-II Pro func-
tional components, as shown in Figure 1:
• Embedded RocketIO™ (up to 3.125 Gb/s) or
RocketIO X (up to 6.25 Gb/s) Multi-Gigabit
Transceivers (MGTs)
• Processor blocks with embedded IBM PowerPC™ 405
RISC CPU core (PPC405) and integration circuitry.
• FPGA fabric based on Virtex-II architecture.
Virtex-II Pro User Guides
Virtex-II Pro User Guides cover theory of operation in more
detail, and include implementation details, primitives and
attributes, command/instruction sets, and many HDL code
examples where appropriate. All parameter specifications
are given only in Module 3 of this Data Sheet.
These User Guides are available:
• For detailed descriptions of PPC405 embedded core
programming models and internal core operations, see
PowerPC Processor Reference Guide and PowerPC
405 Processor Block Reference Guide.
• For detailed RocketIO transceiver digital/analog design
considerations, see RocketIO Transceiver User Guide.
• For detailed RocketIO X transceiver digital/analog
design considerations, see RocketIO X Transceiver
User Guide,
• For detailed descriptions of the FPGA fabric (CLB, IOB,
DCM, etc.), see Virtex-II Pro Platform FPGA User
Guide.
All of the documents above, as well as a complete listing
and description of Xilinx-developed Intellectual Property
cores for Virtex-II Pro, are available on the Xilinx website.
Contents of This Module
• Functional Description: RocketIO X Multi-Gigabit
Transceiver (MGT)
• Functional Description: RocketIO Multi-Gigabit
Transceiver (MGT)
• Functional Description: Processor Block
• Functional Description: Embedded PowerPC 405 Core
• Functional Description: FPGA
• Revision History
Virtex-II Pro Compared to Virtex-II Devices
Virtex-II Pro devices are built on the Virtex-II FPGA archi-
tecture. Most FPGA features are identical to Virtex-II
devices. Major differences are described below:
• The Virtex-II Pro FPGA family is the first to incorporate
embedded PPC405 and RocketIO/RocketIO X cores.
• V_CCAUX, the auxiliary supply voltage, is 2.5V instead of
3.3V as for Virtex-II devices. Advanced processing at
0.13 μm has resulted in a smaller die, faster speed,
and lower power consumption.
• Virtex-II Pro devices are neither bitstream-compatible nor
pin-compatible with Virtex-II devices. However, Virtex-II
designs can be compiled into Virtex-II Pro devices.
• On-chip input LVDS differential termination is available.
• SSTL3, AGP-2X/AGP, LVPECL_33, LVDS_33, and
LVDSEXT_33 standards are not supported.
• The open-drain output pin TDO does not have an
internal pull-up resistor.
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
© 2002–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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