DS083 Datasheet, PDF (82/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Switching Characteristics
Switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Note that Virtex-II Pro Perfor-
mance Characteristics are subject to these guidelines, as
well. Each designation is defined as follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device. Table 15 correlates the current status of each
Virtex-II Pro device with a corresponding speed file desig-
nation.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Table 15: Virtex-II Pro Device Speed Grade Designations
Speed Grade Designations
Device
Advance Preliminary Production
XC2VP2
-7, -6, -5
XC2VP4
-7, -6, -5
XC2VP7
-7, -6, -5
XC2VP20
-7, -6, -5
XC2VPX20
-6, -5
XC2VP30
-7, -6, -5
XC2VP40
-7, -6, -5
XC2VP50
-7, -6, -5
XC2VP70
-7, -6, -5
XC2VPX70
-6, -5
XC2VP100
-6, -5
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotate to the
simulation net list. Unless otherwise noted, values apply to
all Virtex-II Pro devices.
PowerPC Switching Characteristics
Table 16: Processor Clocks Absolute AC Characteristics
Speed Grade
-7
-6
-5
Description
CPMC405CLOCK frequency
JTAGC405TCK frequency⁽²⁾
PLBCLK ⁽³⁾
BRAMDSOCMCLK ⁽³⁾
BRAMISOCMCLK ⁽³⁾
Min
Max
Min
Max
Min
Max
Units
0
400 ⁽¹⁾
0
350 ⁽¹⁾
0
300
MHz
0
200
0
175
0
150
MHz
0
400
0
350
0
300
MHz
0
400
0
350
0
300
MHz
0
400
0
350
0
300
MHz
Notes:
1. IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or
greater than 300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755,
“PowerPC 405 Clock Macro for -7(C) and -6(I) Speed Grade Dual-Processor Devices.” Refer to Table 1, Module 1 to identify
dual-processor devices.
2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is dependent
on the system, and will be much less.
3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. However, the achievable maximum is
dependent on the system. Please see PowerPC 405 Processor Block Reference Guide and XAPP640 for more information.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
11