DS083 Datasheet, PDF (118/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Output Clock Jitter
Table 56: Output Clock Jitter
Speed Grade
Description
Symbol
Constraints
–7
–6
–5 Units
Clock Synthesis Period Jitter
CLK0
CLKOUT_PER_JITT_0
±100 ±100 ±100
ps
CLK90
CLKOUT_PER_JITT_90
±150 ±150 ±150
ps
CLK180
CLKOUT_PER_JITT_180
±150 ±150 ±150
ps
CLK270
CLKOUT_PER_JITT_270
±150 ±150 ±150
ps
CLK2X, CLK2X180
CLKOUT_PER_JITT_2X
±200 ±200 ±200
ps
CLKDV (integer division)
CLKOUT_PER_JITT_DV1
±150 ±150 ±150
ps
CLKDV (non-integer division)
CLKOUT_PER_JITT_DV2
±300 ±300 ±300
ps
CLKFX, CLKFX180
CLKOUT_PER_JITT_FX
Note (1) Note (1) Note (1)
ps
Notes:
1. Use the Jitter Calculator on the Xilinx website (http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm) for CLKFX and
CLKFX180 output jitter.
Output Clock Phase Alignment
Table 57: Output Clock Phase Alignment
Description
Symbol
Constraints
Speed Grade
–7
–6
–5
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
CLKIN_CLKFB_PHASE
±50
±50
±50
Phase Offset Between Any DCM Outputs
All CLK* outputs
CLKOUT_PHASE
±140 ±140 ±140
Duty Cycle Precision
DLL outputs⁽¹⁾
CLKOUT_DUTY_CYCLE_DLL⁽²⁾
±150 ±150 ±150
CLKFX outputs
CLKOUT_DUTY_CYCLE_FX
±100 ±100 ±100
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
3. Specification also applies to PSCLK.
Units
ps
ps
ps
ps
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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