DS083 Datasheet, PDF (36/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table 9: Supported Differential Signal I/O Standards
I/O Standard
LDT_25
Output
V_CCO
2.5
Input
V_CCO
N/R
Input
V_REF
N/R
Output
V_OD
0.500 – 0.740
LVDS_25
2.5
N/R
N/R 0.247 – 0.454
LVDSEXT_25
2.5
N/R
N/R 0.440 – 0.820
BLVDS_25
2.5
N/R
N/R 0.250 – 0.450
ULVDS_25
2.5
N/R
N/R 0.500 – 0.740
LVPECL_25
2.5
N/R
N/R 0.345 – 1.185
LDT_25_DT ⁽¹⁾
2.5
2.5
N/R 0.500 – 0.740
LVDS_25_DT⁽¹⁾
2.5
2.5
N/R 0.247 – 0.454
LVDSEXT_25_DT ⁽¹⁾
2.5
2.5
N/R 0.330 – 0.700
ULVDS_25_DT ⁽¹⁾
2.5
2.5
N/R 0.500 – 0.740
Notes:
1. These standards support on-chip 100Ω termination.
2. N/R = no requirement.
Table 10: Supported DCI I/O Standards
I/O Standard
LVDCI_33 ⁽¹⁾
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
Output
V_CCO
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
Input
V_CCO
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
Input
V_REF
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.75
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
1.5
1.5
0.75
1.5
1.5
0.9
1.5
1.5
0.9
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
1.8
1.8
0.9
1.8
1.8
0.9
1.8
1.8
1.1
HSTL_IV_DCI_18
SSTL2_I_DCI ⁽²⁾
SSTL2_II_DCI⁽²⁾
SSTL18_I_DCI ⁽³⁾
SSTL18_II_DCI
1.8
1.8
1.1
2.5
2.5
1.25
2.5
2.5
1.25
1.8
1.8
0.9
1.8
1.8
0.9
Termination
Type
Series
Series
Series
Series
Series
Series
Series
Single
Single
Split
Split
Single
Single
Split
Split
Single
Single
Split
Split
Split
Split
Table 10: Supported DCI I/O Standards (Continued)
I/O Standard
LVDS_25_DCI
Output
V_CCO
2.5
Input
V_CCO
2.5
Input
V_REF
N/R
Termination
Type
Split
LVDSEXT_25_DCI
2.5
2.5
N/R
Split
Notes:
1. LVDCI_XX is LVCMOS output controlled impedance buffers,
matching all or half of the reference resistors.
2. These are SSTL compatible.
3. SSTL18_I is not a JEDEC-supported standard.
4. N/R = no requirement.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 19.
IOB
Reg
OCK1
DDR mux
Reg
OCK2
3-State
Reg
OCK1
DDR mux
Reg
OCK2
Output
Input
Reg
ICK1
Reg
ICK2
PAD
DS031_29_100900
Figure 19: Virtex-II Pro IOB Block
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 20. There are two input, output,
and 3-state data signals, each being alternately clocked out.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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