DS083 Datasheet, PDF (49/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Figure 36, Figure 37, and Figure 38 illustrate various exam-
ple configurations.
RAM 16x1D
RAM 16x1S
A[3:0] ⁴
4
RAM
A[4:1] D
WG[4:1]
WS DI
D ^(BY)
WE
WCLK
WSG
(SR) _WE
CK
DQ
Output
Registered
Output
(optional)
DS031_02_100900
Figure 36: Distributed SelectRAM+ (RAM16x1S)
A[4]
A[3:0]
(BX)
D ^(BY)
WE ^(SR)
WCLK
RAM 32x1S
RAM
4
G[4:1] D
WG[4:1]
WS DI
WSG
WE0
WE
CK
WSF
F5MUX
WS DI
4
RAM _D
F[4:1]
WF[4:1]
DQ
Output
Registered
Output
(optional)
DS083-2_10_050901
Figure 37: Single-Port Distributed SelectRAM+
(RAM32x1S)
DPRA[3:0]
A[3:0]
D
4
4
(BY)
dual_port
RAM
G[4:1] D
WG[4:1]
WS DI
WSG
WE
CK
DPO
A[3:0]
4
dual_port
RAM
G[4:1] D
WG[4:1]
WS DI
SPO
WE
WCLK
(SR)
WSG
WE
CK
DS031_04_110100
Figure 38: Dual-Port Distributed SelectRAM+
(RAM16x1D)
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are available: ROM16x1, ROM32x1, ROM64x1,
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration. Table 17 shows the
number of LUTs occupied by each configuration.
Table 17: ROM Configuration
ROM
16 x 1
32 x 1
64 x 1
128 x 1
256 x 1
Number of LUTs
1
2
4
8 (1 CLB)
16 (2 CLBs)
DS083 (v4.7) November 5, 2007
Product Specification
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Module 2 of 4
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