DS083 Datasheet, PDF (135/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FG256/FGG256 Fine-Pitch BGA Package
As shown in Table 5, XC2VP2 and XC2VP4 Virtex-II Pro devices are available in the FG256/FGG256 fine-pitch BGA
package. The pins in each of these devices are identical. Following this table are the FG256/FGG256 Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 5: FG256/FGG256 — XC2VP2 and XC2VP4
Bank
Pin Description
0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0
0
IO_L03P_0/VREF_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L07P_0
0
IO_L09N_0
0
IO_L09P_0/VREF_0
0
IO_L69N_0
0
IO_L69P_0/VREF_0
0
IO_L74N_0/GCLK7P
0
IO_L74P_0/GCLK6S
0
IO_L75N_0/GCLK5P
0
IO_L75P_0/GCLK4S
Pin Number
C2
C3
B3
C4
A2
A3
D5
C5
D6
E6
E7
D7
C7
D8
C8
B8
A8
1
IO_L75N_1/GCLK3P
A9
1
IO_L75P_1/GCLK2S
B9
1
IO_L74N_1/GCLK1P
C9
1
IO_L74P_1/GCLK0S
D9
1
IO_L69N_1/VREF_1
C10
1
IO_L69P_1
D10
1
IO_L09N_1/VREF_1
E10
1
IO_L09P_1
E11
1
IO_L07N_1
D11
1
IO_L06N_1
C12
1
IO_L06P_1
D12
1
IO_L03N_1/VREF_1
A14
1
IO_L03P_1
A15
DS083 (v4.7) November 5, 2007
Product Specification
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