DS083 Datasheet, PDF (80/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II Pro devices. The numbers reported here are fully
characterized worst-case values. Note that these values are
subject to the same guidelines as Virtex-II Pro Switching
Characteristics (speed files).
Table 13 provides pin-to-pin values (in nanoseconds)
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
Table 13: Pin-to-Pin Performance
Description
Device Used & Speed Grade
Pin-to-Pin Performance
(with I/O Delays)
Units
Basic Functions:
16-bit Address Decoder
XC2VP20FF1152-6
7.20
ns
32-bit Address Decoder
XC2VP20FF1152-6
8.08
ns
64-bit Address Decoder
XC2VP20FF1152-6
8.15
ns
4:1 MUX
XC2VP20FF1152-6
3.85
ns
8:1 MUX
XC2VP20FF1152-6
7.24
ns
16:1 MUX
XC2VP20FF1152-6
7.30
ns
32:1 MUX
XC2VP20FF1152-6
7.64
ns
Combinatorial (pad to LUT to pad)
XC2VP20FF1152-6
3.26
ns
Memory:
Block RAM
Pad to setup
XC2VP20FF1152-6
1.72
ns
Clock to Pad
XC2VP20FF1152-6
6.63
ns
Distributed RAM
Pad to setup
XC2VP20FF1152-6
1.78
ns
Clock to Pad
XC2VP20FF1152-6
4.12
ns
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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