DS083 Datasheet, PDF (51/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Multiplexers
Virtex-II Pro function generators and associated multiplex-
ers can implement the following:
• 4:1 multiplexer in one slice
• 8:1 multiplexer in two slices
• 16:1 multiplexer in one CLB element (4 slices)
• 32:1 multiplexer in two CLB elements (8 slices)
Each Virtex-II Pro slice has one MUXF5 multiplexer and
one MUXFX multiplexer. The MUXFX multiplexer imple-
ments the MUXF6, MUXF7, or MUXF8, as shown in
Figure 41. Each CLB element has two MUXF6 multiplexers,
one MUXF7 multiplexer and one MUXF8 multiplexer. Exam-
ples of multiplexers are shown in the Virtex-II Pro Platform
FPGA User Guide. Any LUT can implement a 2:1 multi-
plexer.
Slice S3
G
F
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
Slice S2
G
F
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
G
Slice S1
F
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
G
Slice S0
F
MUXF6 combines the two MUXF6
outputs from slices S0 and S1
CLB
Figure 41: MUXF5 and MUXFX multiplexers
DS031_08_110200
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II Pro CLB has two separate carry
chains, as shown in the Figure 42.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II Pro device is running upward. The ded-
icated carry path and carry multiplexer (MUXCY) can also
be used to cascade function generators for implementing
wide logic functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in Figure 34)
improves the efficiency of multiplier implementation.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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