DS083 Datasheet, PDF (214/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 9: FF896 — XC2VP7, XC2VP20, XC2VPX20, and XC2VP30
Pin Description
Bank
Virtex-II Pro devices
XC2VPX20
(if Different)
Pin
Number
7
IO_L36N_7
F27
7
IO_L35P_7
K24
7
IO_L35N_7
K23
7
IO_L34P_7
E30
7
IO_L34N_7/VREF_7
E29
7
IO_L33P_7
E28
7
IO_L33N_7
E27
7
IO_L32P_7
H26
7
IO_L32N_7
H25
7
IO_L31P_7
D30
7
IO_L31N_7
D29
7
IO_L06P_7
D28
7
IO_L06N_7
C27
7
IO_L05P_7
J24
7
IO_L05N_7
J23
7
IO_L04P_7
C30
7
IO_L04N_7/VREF_7
C29
7
IO_L03P_7
D26
7
IO_L03N_7
C26
7
IO_L02P_7
G26
7
IO_L02N_7
G25
7
IO_L01P_7/VRN_7
B28
7
IO_L01N_7/VRP_7
A28
XC2VP7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
No Connects
XC2VP20,
XC2VPX20 XC2VP30
0
VCCO_0
K21
0
VCCO_0
K20
0
VCCO_0
K19
0
VCCO_0
K18
0
VCCO_0
K17
0
VCCO_0
K16
0
VCCO_0
J21
0
VCCO_0
J20
0
VCCO_0
J19
0
VCCO_0
J18
1
VCCO_1
K15
1
VCCO_1
K14
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
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