DS083 Datasheet, PDF (14/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
PACKAGE
PINS
AVCCAUXTX
VTRX
2.5V
Termination Supply RX
MULTI-GIGABIT TRANSCEIVER CORE
Power Down
RXP
RXN
TXP
TXN
Deserializer
Clock
Manager
Serializer
Comma
Detect
Realign
64B/66B
Descrambler
8B/10B
Decoder
RX
Elastic
Buffer
64B/66B
Block Sync
Channel Bonding
and
Clock Correction
Gear
Box
Scrambler
Output
Polarity
TX
FIFO
64B/66B
Encoder
8B/10B
Encoder
GNDA _{TX/RX GND}
AVCCAUXRX _1.5V
VTTX _{Termination Supply TX}
Clock /
Reset
PMA
Attribute
Load
Figure 4: RocketIO X Transceiver Block Diagram
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
FPGA FABRIC
POWERDOWN
RXRECCLK
RXPOLARITY
RXREALIGN
RXCOMMADET
ENPCOMMAALIGN
ENMCOMMAALIGN
RXDATA[63:0]
RXNOTINTABLE[7:0]
RXDISPERR[7:0]
RXCHARISK[7:0]
RXCHARISCOMMA[7:0]
RXRUNDISP[7:0]
RXBUFSTATUS[1:0]
ENCHANSYNC
CHBONDDONE
CHBONDI[4:0]
CHBONDO[4:0]
RXLOSSOFSYNC[1:0]
RXCLKCORCNT[2:0]
TXBUFERR
TXDATA[63:0]
TXBYPASS8B10B[7:0]
TXCHARISK[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXKERR[7:0]
TXRUNDISP[7:0]
TXPOLARITY
TXINHIBIT
LOOPBACK[1:0]
TXRESET
RXRESET
REFCLK
REFCLK2
REFCLKSEL
BREFCLKP
BREFCLKN
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
PMAINIT
PMAREGADDR[5:0]
PMAREGDATAIN[7:0]
PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL[1:0]
PMARXLOCK
REFCLKBSEL
RXBLCOKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH[1:0]
RXDECC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE
RXIGNOREBTF
RXINTDATAWIDTH[1:0]
RXSLIDE
TXDATAWIDTH[1:0]
TXENC64B66BUSE
TXENC8B10BUSE
TXFORCECRCERR
TXGEARBOX64B66BUSE
TXINTDATAWIDTH[1:0]
TXSCRAM64B66BUSE
TXOUTCLK
DS083-2_37_050704
Module 2 of 4
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