DS083 Datasheet, PDF (113/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Table 51: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
Without DCM
Speed Grade
Description
Symbol
Device
-7
-6
-5
Units
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, without DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page 26.
Global Clock and OFF without DCM
T_ICKOF
XC2VP2
3.19
3.52
3.82
ns
XC2VP4
3.39
3.91
4.27
ns
XC2VP7
3.59
4.00
4.36
ns
XC2VP20
3.62
4.08
4.46
ns
XC2VPX20
3.62
4.08
4.46
ns
XC2VP30
3.73
4.12
4.50
ns
XC2VP40
3.89
4.28
4.67
ns
XC2VP50
4.00
4.43
4.84
ns
XC2VP70
4.38
4.87
5.33
ns
XC2VPX70
4.38
4.87
5.33
ns
XC2VP100
N/A
5.32
5.82
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with test setup shown in Figure 6. For other I/O standards, see Table 37.
3. DCM output jitter is already included in the timing calculation.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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