DS083 Datasheet, PDF (114/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Table 52: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Speed Grade
Description
Symbol
Device
-7
-6
-5
Units
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.⁽¹⁾
For data input with different standards,
adjust the setup time delay by the values
shown in IOB Input Switching
Characteristics Standard Adjustments,
page 23.
No Delay
Global Clock and IFF⁽²⁾ with DCM
T_PSDCM/T_PHDCM XC2VP2 _{1.54/–0.58 1.54/–0.57 1.54/–0.56}
ns
XC2VP4 1.59/–0.59 1.59/–0.58 1.59/–0.57
ns
XC2VP7 1.66/–0.61 1.66/–0.59 1.66/–0.57
ns
XC2VP20 1.68/–0.53 1.68/–0.53 1.68/–0.50
ns
XC2VPX20 1.68/–0.53 1.68/–0.53 1.68/–0.50
ns
XC2VP30 1.81/–0.74 1.81/–0.74 1.81/–0.71
ns
XC2VP40 1.85/–0.65 1.85/–0.64 1.85/–0.60
ns
XC2VP50 1.85/–0.57 1.85/–0.54 1.85/–0.50
ns
XC2VP70 1.86/–0.45 1.86/–0.39 1.86/–0.30
ns
XC2VPX70 1.86/–0.45 1.86/–0.39 1.86/–0.30
ns
XC2VP100
N/A
1.86/–0.35 1.87/–0.28
ns
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case duty-cycle distortion using CLK0 and CLK180, T_{DCD_CLK180}.
3. IFF = Input Flip-Flop or Latch
DS083 (v4.7) November 5, 2007
Product Specification
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