DS083 Datasheet, PDF (107/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Block SelectRAM+ Switching Characteristics
Table 44: Block SelectRAM+ Switching Characteristics
Speed Grade
Description
Symbol
-7
-6
-5
Units
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
T_BCKO
1.41
1.50
1.68
ns, max
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
T_BACK/T_BCKA
T_BDCK/T_BCKD
T_BECK/T_BCKE
T_BRCK/T_BCKR
T_BWCK/T_BCKW
0.27/ 0.22
0.20/ 0.22
0.28/ 0.00
0.28/ 0.00
0.33/ 0.00
0.31/ 0.25
0.23/ 0.25
0.32/ 0.00
0.32/ 0.00
0.35/ 0.00
0.35/ 0.28
0.26/ 0.28
0.35/ 0.00
0.35/ 0.00
0.39/ 0.00
ns, min
ns, min
ns, min
ns, min
ns, min
CLKA to CLKB setup time for different ports
T_BCCS
1.0
1.0
1.0
ns, min
Minimum Pulse Width, High
T_BPWH
1.17
1.30
1.50
ns, min
Minimum Pulse Width, Low
T_BPWL
1.17
1.30
1.50
ns, min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
TBUF Switching Characteristics
Table 45: TBUF Switching Characteristics
Description
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
Symbol
T_IO
T_OFF
T_ON
Speed Grade
-7
-6
-5
Units
0.88
1.01
1.12
ns, max
0.48
0.55
0.61
ns, max
0.48
0.55
0.61
ns, max
DS083 (v4.7) November 5, 2007
Product Specification
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