DS083 Datasheet, PDF (127/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Date
11/17/04
03/01/05
06/20/05
Version
4.1
4.2
4.3
Revision
• Figure 8, Figure 9: Corrected T_CCO / DOUT to refer to the falling edge of CCLK.
• Table 23: Added Footnote (4) to T_PHASE indicating an 8B/10B-type bitstream.
Corrected T_LOCK from Typ to Max specification. Additional description of “2X
oversampling” added to half-rate operation condition for F_GCLK, and added Footnote
(2) requiring use of oversampling techniques in XAPP572 for serial bit rates under
1 Gb/s.
• Table 25: Converted bit rate conditions for jitter parameters into four ranges. Added
Footnote (2) requiring use of oversampling techniques in XAPP572 for serial bit rates
under 1 Gb/s.
• Table 27: Additional description of “2X oversampling” added to half-speed clock
description for F_GGTX. Converted bit rate conditions for jitter parameters into four
ranges. Added Footnotes (3) and (4) requiring use of oversampling techniques in
XAPP572 for serial bit rates under 1 Gb/s.
• Table 37: Changed capacitance C_REF for all PCI/PCI-X standards from 0 pF to 10 pF.
• Table 46: Added Min/Max specifications for T_ICCK.
• Section Power-On Power Supply Requirements, page 5: Added word “monotonically”
to description of V_CCINT ramp-on requirements. Removed requirement that V_CCAUX
must be powered on before or with V_CCO.
• Updated values in Virtex-II Pro Performance Characteristics and Virtex-II Pro
Switching Characteristics tables, based on values extracted from speedsfile version
1.90.
• Table 1 and Table 2: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and
AVCCAUXRX respectively.
• Table 3: Further clarified P_RXTX (MGT power dissipation) by explaining measurement
method in Footnote (3).
• Table 5: Added power-on current specifications for XC2VPX70 device.
• Table 22: Changed F_GTOL from ±100 ppm to ±350 ppm.
• Table 22 and Table 23: Changed T_GJTT bit rate qualifiers from fixed bit rates to bit rate
ranges.
• Table 33, Table 35, Table 36, and Table 37: Restructured these I/O-related tables to
include descriptions, as well as the actual IOSTANDARD attributes (used in the Xilinx
ICE™ software) for all I/O standards.
• Table 33: Rearranged I/O standards in a more logical order.
• Table 34: Added parameter T_RPW (Minimum Pulse Width, SR Input).
• Table 35: Changed “Csl” to “C_REF” to agree with Figure 6 and Table 37. Rearranged
I/O standards in a more logical order.
• Table 36: Added footnote defining equivalents for DCI standards.
• Table 37: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C_REF) values.
• Table 44: Added parameter T_BCCS, CLKA to CLKB Setup Time.
• Table 47: Added Footnote (1) indicating that F_{CC_SERIAL} should not exceed
F_{CC_STARTUP} if CCLK frequency is not adjustable.
• Table 49: T_TCKTDO corrected from a “Min” to a “Max” specification.
• Table 12: Added specifications for Differential Input Impedance.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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