DS083 Datasheet, PDF (109/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Master/Slave Serial Mode Parameters
Clock timing for Slave Serial configuration programming is shown in Figure 8, with Master Serial clock timing shown in
Figure 9. Programming parameters for both Slave and Master modes are given in Table 47.
Serial DIN
CCLK
Serial DOUT
1 T_DCC
2 T_CCD
4 T_CCH
5 T_CCL
3 T_CCO
Figure 8: Slave Serial Mode Timing Sequence
ds083-3_08_111104
CCLK
(Output)
Serial DIN
1 T_DSCK
2
T_CKDS
Serial DOUT
Figure 9: Master Serial Mode Timing Sequence
ds083-3_09_111104
.
Table 47: Master/Slave Serial Mode Timing Characteristics
Description
Figure
References
Symbol
Value
Units
DIN setup/hold, slave mode (Figure 8)
1/2
DIN setup/hold, master mode (Figure 9)
1/2
DOUT
3
High time
4
CCLK _{Low time}
5
Maximum start-up frequency
Maximum frequency
Frequency tolerance, master mode with
respect to nominal
T_DCC/T_CCD
T_DSCK/T_CKDS
T_CCO
T_CCH
T_CCL
F_{CC_STARTUP}
F_{CC_SERIAL}
5.0/0.0
5.0/0.0
12.0
5.0
5.0
50
66 ⁽¹⁾
+45%
–30%
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
MHz, max
Notes:
1. If no provision is made in the design to adjust the frequency of CCLK, F_{CC_SERIAL} should not exceed F_{CC_STARTUP}.
DS083 (v4.7) November 5, 2007
Product Specification
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