DS083 Datasheet, PDF (50/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure 39. A dynamic read access is performed through the
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous; how-
ever, the storage element or flip-flop is available to
implement a synchronous read. Any of the 16 bits can be
read out asynchronously by varying the address. The stor-
age element should always be used with a constant
address. For example, when building an 8-bit shift register
and configuring the addresses to point to the 7th bit, the 8th
bit can be the flip-flop. The overall system performance is
improved by using the superior clock-to-out of the flip-flops.
SHIFTIN
SRLC16
A[3:0]
D(BY)
CE (SR)
CLK
SHIFT-REG
4 _A[4:1]
D
MC15
WS
DI
WSG
WE
CK
DQ
Output
Registered
Output
(optional)
SHIFTOUT
DS031_05_110600
Figure 39: Shift Register Configurations
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure 40.) Longer shift registers can be built with dynamic
access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.
1 Shift Chain
in CLB
IN
DI
D
FF
SRLC16
MC15
SLICE S3
DI _D
FF
SRLC16
MC15
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
SLICE S2
DI _D
FF
SRLC16
MC15
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
DI _D
SRLC16
MC15
FF
SLICE S1
SHIFTOUT
SHIFTIN
DI _D
FF
SRLC16
MC15
DI _D
SRLC16
MC15
FF
SLICE S0
OUT
CASCADABLE OUT
CLB
DS031_06_110200
Figure 40: Cascadable Shift Register
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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