DS083 Datasheet, PDF (177/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40
Bank
Pin Description
Pin Number
N/A
GND
R15
N/A
GND
R16
N/A
GND
R24
N/A
GND
T11
N/A
GND
T12
N/A
GND
T13
N/A
GND
T14
N/A
GND
T15
N/A
GND
T16
N/A
GND
U6
N/A
GND
U21
N/A
GND
W4
N/A
GND
W23
N/A
GND
AA10
N/A
GND
AA17
N/A
GND
AC4
N/A
GND
AC8
N/A
GND
AC19
N/A
GND
AC23
N/A
GND
AD3
N/A
GND
AD24
N/A
GND
AE2
N/A
GND
AE25
N/A
GND
AF1
N/A
GND
AF26
Notes:
1. See Table 4 for an explanation of the signals available on this pin.
No Connects
XC2VP20 XC2VP30 XC2VP40
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
49